Chip-to-Wafer Bonding Carrier Stabilization
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Solution Overview
Problem
Current methods for producing 3D Integrated Chips (3D ICs) face challenges such as low throughput, high production costs, and low silicon utilization in Chip-to-Chip (C2C) and Wafer-to-Wafer (W2W) methods, with the Chip-to-Wafer (C2W) method being technically unfeasible due to handling issues and varied temperature requirements.
Innovation Solution
A method for bonding multiple chips onto a base wafer involves fixing the base wafer on a carrier during stacking and heat treatment, allowing for increased throughput by separating process steps and enabling efficient alignment and bonding of chips of different sizes, with the use of a carrier to stabilize and handle the base wafer, and employing inert atmospheres and organic cements to prevent oxidation and improve chip yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the base wafer is made thinner and/or larger in area to increase chip stacking capacity, then the chip stacking density is improved, but the handling difficulty and fracture risk increase
Solution Approach 1:
A support structure is introduced as an intermediary element between the base wafer and the handling system. This support structure provides mechanical reinforcement to thin, large-area base wafers during chip stacking operations, enabling handling of wafers that would otherwise be too fragile while maintaining the desired thin and large dimensions for high stacking capacity.
2Device complexity
If the C2W method is implemented without separating process steps, then the device complexity is reduced, but the throughput decreases due to long heat treatment times
Solution Approach 1:
The chip stacking process is segmented into distinct stages: chip placement on the base wafer, and subsequent heat treatment for bonding. This segmentation allows chip placement to be performed rapidly with high throughput, while heat treatment occurs separately in dedicated chambers, eliminating the bottleneck that would limit overall productivity if both steps were combined.
3Productivity
If multiple heat treatment chambers are used to increase throughput, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The support structure is designed with multi-functionality to accommodate different base wafer sizes and configurations across multiple heat treatment chambers. This universal design allows the same support structure to be used in various chamber types (hot plates, continuous furnaces, modified wafer bonding chambers), enabling throughput enhancement without proportionally increasing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances throughput, improves chip yield, and allows for the handling of thinner, larger base wafers, enabling the production of 3D ICs with high efficiency and reduced scrap, while accommodating chips of varying sizes and facilitating connections to higher-order packing units.
Implementation Method 1
fixing the base wafer on a carrier
Implementation Method 2
heat treatment of the chips (3) on the base wafer (1) fixed to the carrier
Implementation Method 3
employing inert atmospheres and organic cements to prevent oxidation
Data Source
AI summary
Method for bonding a plurality of chips onto a base wafer.