Chip-to-Wafer Bonding Structure Without TSV Die Area Penalty

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Solution Overview

Problem

Existing chip-to-wafer (C2W) integration methods for 3D-IC technology face challenges with through-silicon vias (TSV) occupying significant die area, complicating the bonding process, and making it difficult to ensure mechanical strength and electrical uniformity, especially when TSVs are formed after bonding or when substrates need to be thinned.

Innovation Solution

A method of bonding first die(s) to a wafer without forming TSVs within the first die(s), using an insulating layer and forming holes to create interconnect structures that electrically connect the first metal layer of the die(s) with the second metal layer of the wafer, allowing for area savings and reduced process complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TSVs are formed in the first die(s) for electrical connection, then electrical connection between dies is achieved, but die area is significantly occupied and design complexity increases

Engineering Contradiction:

Improveelectrical connectionVSAvoiddie area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the via formation from the die substrate to the wafer level. Instead of forming TSVs through the die thickness (vertical dimension in die), the method forms holes through the wafer after die bonding, utilizing the wafer's thickness dimension. This dimensional shift eliminates the need for TSVs in the die, freeing up die area while maintaining electrical connection functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent performs die bonding before forming the connection holes. By bonding the first die to the wafer first, then subsequently forming holes through the wafer to expose metal layers, the process eliminates the need for preliminary TSV formation in the die. This sequence reversal (bonding before via formation) is the core preliminary action that resolves the area occupation problem.

Inventive Principle:

Principle #10Preliminary action

2Area of stationary object

If TSVs are formed after die bonding, then die area is saved, but thickness variation control becomes difficult and electrical uniformity is compromised

Engineering Contradiction:

Improvedie areaVSAvoidthickness control

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent uses the wafer as a universal platform that serves multiple functions: as the bonding substrate for the die, as the medium through which connection holes are formed, and as the structure that maintains thickness uniformity. The wafer's large area and structural integrity provide a common reference plane that enables precise hole formation and thickness control across multiple dies, making the wafer a multi-functional element that resolves both area and precision concerns.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Strength

If substrates are made thick to ensure mechanical strength for TSV formation, then mechanical strength is sufficient, but substrate thinning becomes impossible after bonding

Engineering Contradiction:

Improvemechanical strengthVSAvoidsubstrate thinning

Core Design Contradiction:

StrengthVSEase of manufacture

Solution Approach 1:

The patent performs the bonding operation before any thinning or hole formation operations. By bonding the die to the wafer first while the wafer maintains its full thickness and mechanical strength, the process ensures structural integrity during bonding. Subsequently, the wafer can be thinned and holes formed without compromising the already-established bonding, eliminating the constraint that prevented substrate thinning in traditional TSV approaches.

Inventive Principle:

Principle #10Preliminary action

4Reliability

If traditional C2W integration with TSVs is used, then electrical connection is achieved, but process complexity increases due to multiple constraints

Engineering Contradiction:

Improveelectrical connectionVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the traditional process sequence by bonding dies to the wafer first, then forming connection holes through the wafer, rather than forming TSVs in dies before bonding. This inversion simplifies the process by eliminating the need for precise TSV alignment and formation in multiple die layers, reducing process complexity while maintaining reliable electrical connection through the wafer-based hole formation approach.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20240021559A1First chip and wafer bonding method and chip stacking structure

Publication Date: 2024.01.18 WUHAN XINXIN SEMICON MFG CO LTD

AI summary

A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).