Chip-to-Wafer Package Stacking to Minimize Warpage

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Solution Overview

Problem

The conventional fabrication of thin stacked packages is challenging due to warpage and handling issues, leading to increased complexity and cost, particularly in mobile device development where thin package on package (PoP) solutions are essential for thinner form factors.

Innovation Solution

The process of chip to wafer bonding, where components are applied to a carrier with a dielectric material to form a reconstituted wafer, allowing for stacking without demounting, thereby minimizing warpage and handling difficulties, and enabling the use of standard fabrication tools and processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional thinning processes are used before stacking, then thin stacked packages can be achieved, but warpage and handling difficulties increase significantly

Engineering Contradiction:
Improvepackage thicknessVSAvoidhandling ease
Core Design Contradiction:
Length of moving objectVSEase of operation

Solution Approach 1:

The patent applies preliminary action by performing the thinning operation after stacking rather than before. Multiple dies are stacked at their full thickness using standard handling procedures, and only the final stacked package is thinned to the desired thickness. This reverses the conventional sequence and avoids handling thin individual dies during assembly.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple thick dies into a single stacked assembly before thinning. By combining the dies while they are still thick and rigid, the assembly maintains structural integrity during handling and stacking operations. The thinning process then acts on the entire stack as one unit rather than on individual thin dies.

Inventive Principle:
Principle #5Merging (Combining)

2Stability of the object's composition

If additional processes like TCNCP or molded underfill are used to address warpage, then stacking stability improves, but fabrication complexity increases

Engineering Contradiction:
Improvestacking stabilityVSAvoidfabrication complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent uses preliminary action by stacking dies at full thickness before thinning, which inherently provides stacking stability without requiring additional underfill processes. The thick dies are rigid and easy to align, eliminating the need for TCNCP or molded underfill to compensate for warpage issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and eliminates the need for complex underfill processes by changing the sequence of operations. By stacking before thinning, the invention removes the requirement for TCNCP, molded underfill, or other warpage compensation techniques, thereby reducing fabrication complexity while maintaining stacking stability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Length of moving object

If thin dies are handled during fabrication, then thin package stacking is achieved, but yield loss due to handling problems increases

Engineering Contradiction:
Improvepackage thicknessVSAvoidfabrication yield
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by completing all stacking operations with thick dies before thinning. This ensures that all handling, alignment, and bonding operations occur with rigid, easy-to-manipulate thick dies, maximizing yield. The thinning operation is performed once on the finished stack, eliminating repeated handling of thin components.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple dies into a thick-stack assembly that is handled as a single unit. This combination allows the entire stack to be manipulated with the rigidity and ease of handling thick components, avoiding the yield losses associated with handling individual thin dies through multiple fabrication steps.

Inventive Principle:
Principle #5Merging (Combining)

4Device complexity

If standard fabrication tools and processes are used, then device complexity is reduced, but achieving thin stacked packages becomes more difficult

Engineering Contradiction:
Improvefabrication complexityVSAvoidpackage thickness
Core Design Contradiction:
Device complexityVSLength of moving object

Solution Approach 1:

The patent uses preliminary action by stacking dies at full thickness using standard fabrication tools and processes, then thinning the completed stack to achieve the desired thin profile. This approach allows the use of conventional equipment for stacking operations while still achieving thin final packages through the post-stack thinning operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional fabrication sequence by stacking before thinning rather than thinning before stacking. This inversion allows standard fabrication tools to be used for the stacking operations with thick dies, while the final thinning step achieves the required thin package dimensions without requiring specialized equipment for handling thin components during assembly.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for the efficient stacking of multiple layers with minimal tilt and parallel processing, reducing yield loss and cost by avoiding the handling of thin dies and enabling very thin stacking heights with improved stability and precision.

Implementation Method 1

Thermal Compression with Non-Conductive Paste (TCNCP)

Methodology Applied
Scientific EffectThermal compression bonding:

Data Source

PatentUS20240213225A1Package stacking using chip to wafer bonding
Publication Date: 2024.06.27 INTEL CORP
  • US20240213225A1 patent drawing
  • US20240213225A1 patent drawing
  • US20240213225A1 patent drawing

AI summary

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.