Chip-to-Wafer Package Stacking for Thin Die Warpage Control
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Solution Overview
Problem
Conventional package stacking processes face challenges in handling very thin dies or packages due to warpage and stiffness, leading to increased complexity and yield loss, particularly in thin package on package (PoP) or staged chip solutions.
Innovation Solution
A chip-to-wafer bonding process that involves building a reconstituted wafer with dies and components on a carrier, applying dielectric material, and thinning layers without demounting, allowing for parallel processing and minimizing warpage issues, enabling multiple layers with uniform thickness and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional thinning and stacking processes are used, then thin package stacking is achieved, but warpage and stiffness issues increase handling complexity and yield loss
Solution Approach 1:
The patent applies preliminary action by performing chip-to-wafer bonding before thinning the package layers. By bonding the chips to the carrier wafer first and then thinning the entire stacked structure together, the process avoids handling very thin individual dies during fabrication. This sequence reversal eliminates warpage issues that occur when thinning is performed before stacking, as the bonded structure provides mechanical stability throughout the thinning process.
Solution Approach 2:
The patent merges multiple operations into a unified process flow where chips are bonded to a carrier wafer, multiple layers are stacked, and then the entire assembly is thinned together in one operation. This combining of bonding, stacking, and thinning operations into a coordinated sequence eliminates the need for separate handling of thin intermediate layers, reducing both process complexity and yield loss from handling damage.
2Reliability
If additional processes like TCNCP or molded underfill are used to handle thin dies, then handling stability improves, but fabrication complexity and cost increase
Solution Approach 1:
The patent performs chip-to-wafer bonding on thick carrier wafers before thinning, which provides inherent mechanical support and stability during all subsequent processing steps. This preliminary bonding action eliminates the need for additional underfill processes or special handling procedures, as the thick carrier wafer serves as a rigid substrate that prevents warpage and handling damage throughout fabrication.
Solution Approach 2:
The patent extracts and eliminates the need for complex additional processes like TCNCP or molded underfill by using chip-to-wafer bonding on thick carriers. The carrier wafer itself provides the mechanical support function that would otherwise require separate underfill processes, simplifying the overall fabrication workflow while maintaining handling stability.
3Length of moving object
If very thin dies are handled during fabrication, then thin package stacking is achieved, but yield loss increases due to handling problems
Solution Approach 1:
The patent performs chip-to-wafer bonding while chips are still mounted on their original thick carriers, before any thinning occurs. This preliminary bonding action creates a mechanically robust structure that can be handled and processed without risk of damage. The thinning operation is then performed on the entire bonded assembly, eliminating the need to handle very thin individual dies at any point during fabrication, thus preventing yield loss from handling damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the fabrication of very thin package stacks with minimal handling issues, achieving parallel layers and reducing the complexity and cost associated with conventional thin die handling processes.
Implementation Method 1
A method includes attaching one or more dies and components in a first stacked layer, a carrier being mounted to a front side of the first stacked layer; molding a first dielectric layer over the one or more dies and components of the first stacked layer; thinning the first stacked layer to a first thickness; attaching one or more dies and components in a second stacked layer; and molding a second dielectric layer over the one or more dies and components of the second stacked layer.
Data Source
AI summary
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.