Chip-to-Wafer Package Stacking for Thin Die Warpage Control
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Solution Overview
Problem
The handling of very thin dies or packages in fabrication is challenging due to warpage and stiffness issues, leading to increased complexity and cost in device fabrication, particularly in thin package on package (PoP) or staged chip solutions for mobile devices.
Innovation Solution
The process of chip to wafer bonding, where components are applied to a carrier with a dielectric material to form a reconstituted wafer, which is then thinned and stacked without demounting from the carrier, minimizing warpage and handling issues by maintaining stability through additional layer buildup and using standard fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional thinning processes are used before stacking, then thin package height is achieved, but warpage and handling difficulty increase significantly
Solution Approach 1:
The patent applies preliminary action by performing the thinning operation after the stacking process is complete, rather than before. The components are first stacked in their full thickness to create a stable aggregate, and then the entire stack is thinned together as a unified structure. This preliminary stacking before thinning avoids the handling difficulties of individual thin components.
Solution Approach 2:
The patent merges multiple components into a single stacked aggregate structure before the thinning operation. By combining several components into one unified stack, the structural stability is improved and warpage is reduced during subsequent processing. The merged structure is then thinned as a single unit rather than handling separate thin components.
2Stability of the object's composition
If additional processes like TCNCP or molded underfill are used to address warpage, then package stability improves, but fabrication complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for additional specialized processes like TCNCP or molded underfill by changing the sequence of operations. Instead of adding these complex processes to address warpage, the invention removes the root cause by stacking before thinning, thereby simplifying the fabrication process while maintaining package stability.
Solution Approach 2:
The patent changes the temporal parameter of the thinning operation, moving it from before stacking to after stacking. This parameter change in the process sequence fundamentally alters the structural behavior during fabrication, providing stability without requiring additional complex processes or materials.
3Length of moving object
If very thin dies are handled in fabrication, then thin package on package structures are achieved, but yield loss due to handling problems increases
Solution Approach 1:
The patent combines multiple dies into a stacked aggregate structure before thinning, so that the handling and processing are performed on a thicker, more robust combined structure rather than individual thin dies. This merging approach maintains higher fabrication yield by avoiding handling problems associated with very thin individual dies.
Solution Approach 2:
The patent performs the stacking operation preliminarily before thinning, creating a stable structure that can be handled and processed with higher yield. The preliminary stacking ensures that subsequent thinning operations are performed on a supported aggregate rather than fragile individual components.
Data Source
AI summary
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.


