Semiconductor Chip Wettable Flanks via Trench Metallization

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Solution Overview

Problem

Existing methods for manufacturing surface-mount chips with wettable flanks are inadequate, particularly in ensuring effective soldering and visual inspection in applications like automotive and medical fields, as the connection metallizations do not extend sufficiently to the chip flanks.

Innovation Solution

A method involving forming trenches on a semiconductor substrate to separate integrated circuits, depositing resin to cover and planarize metallizations, and creating openings to expose wettable flanks, allowing for extended metallization exposure and improved soldering quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If connection metallizations are formed on the semiconductor substrate, then electrical connections between integrated circuits are established, but the metallizations do not extend to the chip flanks making visual inspection of soldering quality impossible

Engineering Contradiction:
Improvesoldering qualityVSAvoidvisual inspection capability
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent extends metallizations from the traditional planar surface onto the vertical flanks of the chip by forming trenches and filling them with additional metallization layers. This three-dimensional extension allows soldering material to rise onto the flanks during reflow soldering, enabling visual inspection of soldering quality from the side of the chip rather than only from the top surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If trenches are formed to extend metallizations to the flanks, then wettable flanks are created for visual inspection, but the manufacturing process complexity increases

Engineering Contradiction:
Improveconnection qualityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent forms trenches and prepares the metallization structures before the final soldering process. By pre-extending the metallizations onto the flanks and creating the wettable flank geometry in advance, the subsequent soldering process becomes simpler and more reliable, as the soldering material can naturally rise onto the pre-prepared flank surfaces during reflow.

Inventive Principle:
Principle #10Preliminary action

3Difficulty of detecting and measuring

If metallizations are extended onto chip flanks, then visual inspection of soldering becomes possible, but the chip structure becomes more complex

Engineering Contradiction:
Improvesoldering inspection capabilityVSAvoidchip structure
Core Design Contradiction:
Difficulty of detecting and measuringVSShape

Solution Approach 1:

The patent utilizes the vertical dimension of the chip flanks to extend metallizations, transforming a two-dimensional surface metallization into a three-dimensional structure that includes vertical sidewalls. This dimensional extension provides access to the solder joint from the side, enabling visual inspection without altering the fundamental planar footprint of the chip.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11881413B2Method for manufacturing electronic chips
Publication Date: 2024.01.23 STMICROELECTRONICS (TOURS) SAS
  • US11881413B2 patent drawing
  • US11881413B2 patent drawing
  • US11881413B2 patent drawing

AI summary

A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.