Semiconductor Chip Wiring Layout for Short-Circuit Current Suppression
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Solution Overview
Problem
The existing semiconductor device technology experiences reduced short circuit capability due to induced electromotive forces counteracting each other in gate and emitter wiring, leading to suppressed gate voltage suppression and increased short circuit current.
Innovation Solution
The semiconductor device configuration includes first and second emitter wiring arranged in parallel on the same side, with the gate wiring positioned on the opposite side, allowing induced electromotive forces to suppress short circuit current effectively, thereby enhancing short circuit capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate wiring and second emitter wiring are arranged in parallel on the same side, then mutual induction can generate induced electromotive force to suppress increase in gate voltage, but the induced electromotive force in gate wiring counteracts the induced electromotive force in second emitter wiring, reducing short circuit capability
Solution Approach 1:
The patent divides the wiring arrangement into distinct spatial groups: gate wiring on one side and emitter wiring on the other side, separated by the semiconductor chip. This segmentation prevents the harmful counteracting effect while preserving the beneficial mutual induction in the emitter wiring.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement where gate and emitter wirings could be parallel, to a three-dimensional arrangement where they are positioned on opposite sides of the semiconductor chip. This dimensional change eliminates the counteracting effect while maintaining the mutual induction benefit.
2Reliability
If induced electromotive force is generated in gate wiring to counteract induced electromotive force in second emitter wiring, then gate voltage suppression effect is reduced, but this configuration was previously used to balance electromagnetic effects
Solution Approach 1:
The patent extracts the gate wiring from the parallel arrangement with emitter wiring and positions it on the opposite side of the semiconductor chip. This extraction eliminates the harmful counteracting effect while simplifying the overall wiring arrangement.
3Reliability
If second wiring and third wiring are arranged in parallel on the same side, then induced electromotive force can be generated to suppress short circuit current, but gate wiring positioned nearby experiences counteracting induced electromotive force
Solution Approach 1:
The patent segments the wiring into distinct spatial zones: emitter wirings (second and third) on one side of the semiconductor chip and gate wiring on the opposite side. This segmentation allows the emitter wirings to generate beneficial induced electromotive force while preventing gate wiring from experiencing harmful counteraction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the increase in short circuit current, improving the semiconductor device's short circuit capability by isolating induced electromotive forces in the second emitter wiring, preventing counteraction with gate wiring.
Implementation Method 1
generating, due to mutual induction from first emitter wiring, an induced electromotive force in second emitter wiring during switching operation
Implementation Method 2
The induced electromotive force is generated not only in the second emitter wiring but also in gate wiring due to mutual induction from the first emitter wiring
Data Source
AI summary
A semiconductor device includes: a first circuit pattern, a second circuit pattern, a third circuit pattern, and a fourth circuit pattern; a semiconductor chip and a first electrode arranged on the first circuit pattern; a second electrode disposed on the second circuit pattern; a third electrode disposed on the third circuit pattern; and a fourth electrode disposed on the fourth circuit pattern, a pad disposed on the semiconductor chip and the second circuit pattern are connected via first wiring, a surface of the semiconductor chip and the third circuit pattern are connected via second wiring, the surface of the semiconductor chip and the fourth circuit pattern are connected via third wiring, the second wiring and the third wiring are arranged on the same side of the surface of the semiconductor chip and in parallel with each other, and the first wiring is disposed on an opposite side from the third wiring.