Chiplet Power Management Engine With Asynchronous Droop Detection
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Solution Overview
Problem
Conventional power management systems in 3D-IC packages with multiple chiplets lack efficient dynamic power management, leading to asynchronous voltage droop behaviors due to impedance mismatches, which can result in functional failures and prolonged recovery times.
Innovation Solution
A power management engine that utilizes a droop detector with superior performance metrics to control clock modulation across chiplets, incorporating bypass modes to manage voltage droops dynamically and asynchronously, ensuring synchronized droop detection and mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each chiplet has its own droop detector to independently monitor voltage levels, then the system can detect voltage droops at different times according to each chiplet's impedance characteristics, but this causes asynchronous detection and complicates coordinated power management
Solution Approach 1:
The patent merges the droop detection functions of multiple chiplets into a single shared droop detector. This unified detector monitors voltage droops across all chiplets asynchronously without requiring synchronization, thereby maintaining detection accuracy while significantly reducing the coordination complexity of managing multiple independent detectors.
Solution Approach 2:
The shared droop detector acts as an intermediary between the voltage supply and individual chiplets. It detects voltage droops and generates clock modulation enable signals that are then distributed to multiple chiplets, eliminating the need for direct peer-to-peer coordination between chiplets and simplifying the overall power management architecture.
2Device complexity
If a single chiplet's droop detector controls clock modulation for all chiplets, then power management is simplified, but the system must account for worst-case droop scenarios among chiplets with varying impedance characteristics
Solution Approach 1:
The system performs preliminary action by having each chiplet continuously monitor its own voltage levels through its droop detector, even when not actively controlling clock modulation. This ensures that when a chiplet experiences worst-case droop conditions, the system already has detection capability in place and can respond appropriately, maintaining reliability without requiring complex real-time coordination.
3Reliability
If chiplets with worse impedance observe higher and quicker droop, then voltage droop mitigation must account for worst-case scenarios, but implementing comprehensive monitoring for all chiplets increases system complexity
Solution Approach 1:
The patent combines the monitoring infrastructure into a single shared droop detector that serves all chiplets. This unified detector captures voltage droop events across the entire power supply network, ensuring worst-case scenarios are covered without requiring separate monitoring circuits for each chiplet, thereby maintaining reliability while minimizing infrastructure complexity.
Data Source
AI summary
Methods, systems, and devices for providing power management using a power management engine of a semiconductor system are described. Power management can refer to power management techniques associated with a semiconductor component (e.g., chiplet). The power management engine supports monitoring power usage and dynamically adjusting power-related parameters to meet a chiplet's performance requirements. In particular, the power management engine supports asynchronous voltage droop detection among chiplets in an integrated circuit, where asynchronous detection denotes that droop events are detected at different times or rates by individual chiplets, without being synchronized. In operation, voltage levels associated with a shared power supply of the first chiplet and a second chiplet are monitored at a first droop detector of a first chiplet. A first voltage droop that triggers a first clock modulation enable signal is detected. The first clock modulation enable signal is communicated to the second chiplet having a second droop detector.