Chiplet Boot Sequencing for Secure Interconnect Initialization

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Solution Overview

Problem

The challenge lies in developing effective booting methods for electronic devices comprising multiple chiplets, which require efficient inter-chiplet communication and secure firmware integrity checks to ensure stability and security.

Innovation Solution

The proposed solution involves an electronic device with a main chiplet and sub-chiplets, where the main chiplet initializes interfaces, acquires external boot firmware, sets inter-chiplet configurations, and loads applications or operating systems, while sub-chiplets perform similar initialization and integrity checks using immutable sources for security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple chiplets are used to achieve functionality division and miniaturization, then manufacturing yield and cost are improved, but system complexity and booting difficulty increase

Engineering Contradiction:

Improvemanufacturing yieldVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system is divided into a main chiplet and multiple sub-chiplets, each with specific functionalities. The main chiplet contains a processor and first memory for executing boot firmware, while sub-chiplets contain second memory for storing additional boot firmware. This segmentation allows independent manufacturing and testing of each chiplet, improving yield while managing complexity through modular architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A silicon interposer is introduced as an intermediary component to connect the main chiplet and sub-chiplets. The interposer provides standardized interconnect interfaces (such as UCIe) that simplify the connection complexity between chiplets, enabling scalable system configuration without proportionally increasing interconnection complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If boot firmware is distributed across multiple chiplets, then system functionality and flexibility are improved, but booting reliability and security become more difficult to ensure

Engineering Contradiction:

Improvesystem flexibilityVSAvoidbooting reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary integrity verification of boot firmware before execution. The main chiplet verifies the integrity of first boot firmware stored in its first memory, and verifies second boot firmware stored in sub-chiplet memories, before loading and executing them. This preliminary verification ensures reliability even though firmware is distributed across multiple chiplets.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the main chiplet monitors the booting process of sub-chiplets and can initiate recovery procedures if abnormalities are detected. The sub-chiplets provide status feedback during initialization, allowing the main chiplet to verify proper operation and maintain system reliability.

Inventive Principle:

Principle #23Feedback

3Ease of operation

If inter-chiplet communication interfaces are initialized during booting, then system operational capability is improved, but booting time and power consumption increase

Engineering Contradiction:

Improvesystem operational capabilityVSAvoidbooting time

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The main chiplet initializes the inter-chiplet communication interface (first interface) during the early boot phase before loading and executing application firmware. By performing this initialization preliminarily, the system ensures operational capability is established before full operation begins, reducing delays during actual usage while managing booting time through efficient sequencing.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient booting and secure operation of electronic devices with multiple chiplets, ensuring stability, security, and easy health checking with alternative processes if abnormalities are detected.

Implementation Method 1

at least one of the main chiplet or the at least one sub-chiplet may be configured to perform a phase-locked loop (PLL) control operation to adjust a clock frequency

Methodology Applied

Scientific EffectPhase-locked loop:

Data Source

PatentUS12248371B1Electronic device having a plurality of chiplets and method for booting thereof

Publication Date: 2025.03.11 REBELLIONS INC

AI summary

An electronic device comprises a main chiplet including a first memory and at least one sub-chiplet including a second memory, wherein the main chiplet is configured to initialize a first interface for inter-chiplet connection based on first boot firmware stored in the first memory in response to receiving booting signal, acquire third boot firmware stored in an external memory, initialize a second interface for communication between an external device and the main chiplet based on the third boot firmware, set a configuration for interconnection between the main chiplet and the at least one sub-chiplet, initialize a third memory included in the main chiplet, and load at least one of an application firmware or an operating system to the third memory, and the at least one sub-chiplet is configured to initialize the first interface based on second boot firmware stored in the second memory in response to receiving the booting signal.