Chiplet Bump Plane Releveling for Uniform 3D Bonding
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Solution Overview
Problem
The complexity of microelectronic component design, driven by demands for smaller, faster, and higher-capacity ICs, leads to challenges in creating a level bonding surface for chip-to-chip interconnections, particularly with the use of chiplets and through-silicon vias, which complicates the reconfiguration of bump planes in 3D stacking.
Innovation Solution
A method involving the bonding of chiplets to a chip using through-silicon vias, followed by patterning and plating of posts to create a level surface, with additional steps including passivation, seed layer application, and the use of photo resist layers to form a single-level bump plane suitable for subsequent bonding, utilizing techniques like compression molding and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chiplets are bonded to a chip using through-silicon vias to increase integration capacity, then the storage capacity and functionality are improved, but the bonding surface becomes uneven making subsequent bonding difficult
Solution Approach 1:
A planarization layer is introduced as an intermediary between the chiplets and subsequent bonding layers. This layer fills the gaps and uneven surfaces created by through-silicon via interconnections, providing a flat bonding surface for additional components while preserving the high integration capacity achieved through chiplet stacking.
2Adaptability or versatility
If multiple advanced nodes and blocks are incorporated into the IC design to increase functionality, then the device capabilities are improved, but the design complexity and structural issues increase
Solution Approach 1:
The IC design is segmented into modular chiplets that can be independently designed, manufactured, and tested. Each chiplet represents a functional block or advanced node, allowing complex functionality to be divided into manageable units. This segmentation reduces overall design complexity while maintaining high adaptability and versatility.
3Volume of moving object
If 3D stacking is used to decrease component size and increase capacity, then the footprint is reduced, but the reconfiguration of bump planes becomes more complex
Solution Approach 1:
The bump plane reconfiguration is performed as a preliminary action during the chiplet packaging process. By integrating the reconfiguration steps into the initial bonding and packaging operations, the complexity of bump plane management is addressed upfront rather than requiring additional complex operations later in the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reconfiguration of bump planes to create a uniform surface for further bonding, enhancing the integration of advanced blocks like SerDes and memory chips, improving the efficiency and capacity of microelectronic structures while maintaining a stable and functional IC design.
Implementation Method 1
The interconnections extend from the surface of the chip through the smaller chiplets by way of through silicon vias
Implementation Method 2
A plurality of openings are created in the photo resist layer exposing the through silicon via interconnects
Implementation Method 3
The patterning may be followed by plating a plurality of posts such that the posts are disposed in the openings
Data Source
AI summary
An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.