Chiplet Interface Bus Scaling for Mixed Bandwidth Communication
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Solution Overview
Problem
Existing electronic systems with multiple communicative electronic chips face inefficiencies due to the lack of versatility in chiplet interfaces, leading to costly and inefficient data processing when different chiplets have varying data bandwidth capabilities.
Innovation Solution
The implementation of advanced interface bus technologies such as AIB 2.0 and AIB-O, which allow for scalable die-to-die communication by using different physical layers with varying data bandwidth densities, while maintaining the same communication protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high data bandwidth interface is used for all chiplets, then data processing speed is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by allowing different chiplets to have different interface configurations matched to their specific bandwidth requirements. High-bandwidth chiplets use advanced interface bus while lower-bandwidth chiplets use standard interfaces, optimizing both performance and cost for each local component rather than forcing uniform high-spec interfaces across all chiplets.
Solution Approach 2:
The patent changes the bandwidth parameter of the interface based on chiplet requirements. The system supports multiple bandwidth modes (e.g., 256 Gbps, 128 Gbps, 64 Gbps) and selects the appropriate interface configuration for each chiplet, allowing the same physical interface to operate at different bandwidth levels to match chiplet capabilities.
2Adaptability or versatility
If high data bandwidth interface is used for all chiplets, then communication capability is improved, but system cost increases
Solution Approach 1:
The patent implements universality by designing a communication system that can handle multiple bandwidth requirements through a single standardized interface architecture. The advanced interface bus can operate at different bandwidth levels (256 Gbps, 128 Gbps, 64 Gbps) and is compatible with various chiplet types, providing multi-functional capability that reduces system complexity and cost.
Solution Approach 2:
The system dynamically adapts the interface bandwidth based on the specific chiplet being communicated with. The interface can switch between different operational modes (full bandwidth, half bandwidth, quarter bandwidth) depending on the partner chiplet's capabilities, providing dynamic versatility without requiring separate dedicated interfaces for each bandwidth level.
3Productivity
If different interface types are used for different chiplets, then interface optimization is improved, but system complexity increases
Solution Approach 1:
The patent segments the interface functionality into a standardized advanced interface bus protocol layer and variable bandwidth physical layer. This segmentation allows the complex protocol handling to be standardized and reused across all chiplets, while only the physical layer needs to be configured for specific bandwidth levels, reducing overall system complexity despite supporting multiple bandwidths.
Solution Approach 2:
The advanced interface bus protocol acts as an intermediary layer that mediates between different bandwidth-capable chiplets. It provides a standardized communication framework that handles protocol complexity, allowing chiplets with different bandwidth capabilities to communicate through a unified interface without each chiplet needing to implement multiple specialized interface types.
Data Source
AI summary
A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.