Multi-Chiplet Cache Chains for Lower-Pin Boot Access
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Solution Overview
Problem
The increased number of central processing units (CPUs) in multi-chiplet modules (MCMs) requiring booting during initialization leads to a significant increase in package pins and costs due to the need for multiple external flash memories, undercutting the advantages of using MCMs over traditional system on chips.
Innovation Solution
A multi-chiplet module system where chiplets are serially coupled to form a chain, with each chiplet having a local cache, allowing data to propagate through local caches, reducing the need for direct memory access and minimizing memory requests, and utilizing a local cache arbitrator to manage concurrent requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If each chiplet is directly coupled to external flash memory, then memory access speed is improved, but device complexity and cost increase due to increased package pins and multiple external flash memories
Solution Approach 1:
The patent segments the memory access function by introducing local caches at different levels (chiplet-level caches and intermediary caches) that divide the memory access task into hierarchical stages, allowing chiplets to access frequently used data locally without directly accessing external flash memory
Solution Approach 2:
The patent introduces intermediary caches between the chiplets and external flash memory. These intermediary caches act as mediators that store copies of boot data and operational data, reducing the need for direct chiplet-to-external-memory access and thereby reducing package pins and external flash memory requirements
2Reliability
If multiple external flash memories are provided for each chiplet, then reliability is improved, but cost increases due to additional components and circuit board requirements
Solution Approach 1:
The patent merges the memory storage function by having multiple chiplets share a single external flash memory through the intermediary cache system. The intermediary caches create a shared memory pool that serves multiple chiplets, eliminating the need for dedicated external flash memories for each chiplet while maintaining boot reliability
Solution Approach 2:
The intermediary caches provide multi-functionality by serving as both local memory for boot data and as a sharing mechanism for operational data across multiple chiplets. This universal cache structure replaces the need for multiple dedicated external flash memories
3Productivity
If data is propagated through local caches in a chiplet chain, then productivity is improved through efficient memory access, but device complexity increases due to cache management requirements
Solution Approach 1:
The patent applies preliminary action by pre-loading boot data and frequently accessed operational data into local caches and intermediary caches during system initialization. This pre-positioning of data in the cache hierarchy eliminates the need for repeated accesses to external flash memory during chiplet booting and operation
Data Source
AI summary
A multi-chiplet module system, method and device including a memory storing chiplet operational data and a plurality of chiplets serially operably coupled to each other forming a chiplet chain. The chiplets in the middle and at one end of the chain each include a local cache with the chiplet at the one end of the chain coupling with the memory. When one of the chiplets requires data stored on the memory it checks the local cache (if it has one), and if not in the local cache, it then queries the cache of the next chiplet in the chain until the required data is propagated from the memory up the caches of the chain to the requesting chiplet.