Interleaved Chiplet Cache Shadow Tags Using Source ID Indexing
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Solution Overview
Problem
Existing graphics processing unit (GPU) and accelerator hardware architectures face challenges in efficiently managing shadow tags for interleaved chiplet caches without requiring additional storage as the number of interleaved caches changes, which is necessary for improved performance and manufacturing yields.
Innovation Solution
An indexing scheme that repurposes address bits by incorporating source chiplet IDs into shadow tags, allowing flexible management of interleaved caches without increasing storage requirements, by swapping static address bits with source chiplet IDs such as stack, die, or channel IDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional storage is allocated for shadow tags in interleaved caches, then shadow tag management capacity increases, but storage requirements and device complexity increase
Solution Approach 1:
The patent merges the shadow tag storage with the existing cache structure by utilizing the same physical storage resources. Instead of allocating separate additional storage for shadow tags, the system combines shadow tag management with the cache interleave structure, allowing shadow tags to be stored within the existing cache framework without increasing overall storage requirements.
Solution Approach 2:
The patent makes the existing cache storage structure serve multiple functions: it stores both cache data and shadow tags simultaneously. The same storage resources that hold cache lines also hold the corresponding shadow tags, eliminating the need for dedicated shadow tag storage and reducing device complexity while maintaining adequate shadow tag management capacity.
2Productivity
If the number of interleaved caches increases, then cache capacity and performance improve, but shadow tag management complexity increases
Solution Approach 1:
The patent implements a dynamic shadow tag management approach where the shadow tag structure adapts to the number of interleaved caches. The system dynamically determines shadow tag indexing and storage based on the actual interleave configuration, allowing the shadow tag management complexity to scale with the number of caches while maintaining efficient performance. This dynamic adaptation prevents static over-provisioning of shadow tag resources.
Solution Approach 2:
The patent segments the shadow tag management into distinct components that correspond to the interleaved cache structure. Each interleaved cache has its own shadow tag subset, and the system manages these segments independently through structured indexing. This segmentation allows the complexity to be distributed and managed locally for each cache segment rather than requiring centralized management of all shadow tags simultaneously.
3Device complexity
If shadow tags are stored without incorporating source chiplet IDs, then storage structure remains simple, but shadow tag collision and incorrect tag matching increase
Solution Approach 1:
The patent nests the source chiplet ID information within the shadow tag structure itself. Rather than storing chiplet IDs separately or using them as external indices, the chiplet ID bits are embedded directly into the shadow tag fields. This nesting allows the shadow tag to contain both the address information and the source chiplet identification in a unified structure, maintaining storage simplicity while ensuring reliable tag matching through the embedded chiplet ID.
Solution Approach 2:
The patent incorporates source chiplet IDs into the shadow tag formation process at the time of tag creation, before any potential tag conflicts can occur. By pre-embedding the chiplet ID information in the shadow tag structure during the initial tagging operation, the system ensures that subsequent tag comparisons automatically include chiplet identification, preventing collisions from different chiplets without requiring additional lookup or verification steps.
Data Source
AI summary
The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.