Chiplet Interposer Capacitor Layout for Noise-Stable Data Links
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Solution Overview
Problem
Current semiconductor chiplet devices face challenges in maintaining power integrity and signal quality due to noise interference, especially in high-performance computing and AI applications where multiple dies are connected through interposer layers.
Innovation Solution
The semiconductor chiplet device incorporates an interposer layer with at least one decoupling capacitor arranged between the interfaces of the first and second dies, or in the vertical projection area of these interfaces on the package substrate, to form a discharge path that eliminates noise and maintains power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple dies are connected through an interposer layer for high-performance computing and AI applications, then data transmission capability is improved, but noise interference increases and power integrity deteriorates
Solution Approach 1:
The patent introduces decoupling capacitors as intermediary elements between the first and second dies through the interposer layer. These capacitors act as mediators that filter noise from power supply lines and signal lines, allowing high-speed data transmission while maintaining power integrity and reducing noise interference in the multi-die system.
Solution Approach 2:
The patent extracts and isolates noise interference from the main signal transmission path by positioning decoupling capacitors in specific locations within the interposer layer. The capacitors capture and remove noise components from power and signal lines, separating harmful noise effects from the beneficial data transmission function.
2Reliability
If decoupling capacitors are added to the interposer layer or package substrate, then power integrity is improved and noise is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by positioning decoupling capacitors at specific locations within the interposer layer or package substrate, particularly in the vertical projection area between the first and second dies. This localized placement ensures that power integrity is improved only where needed, rather than requiring capacitors throughout the entire device structure.
Solution Approach 2:
The patent implements partial action by using at least one decoupling capacitor in the interposer layer or package substrate, rather than requiring a complete network of capacitors throughout the system. This minimal sufficient approach provides adequate noise filtering and power integrity improvement without unnecessarily increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of decoupling capacitors effectively reduces noise interference, ensures power supply stability, and optimizes power integrity in semiconductor chiplet devices, enhancing their performance in HPC and AI applications.
Implementation Method 1
The interposer layer comprises at least one decoupling capacitor, the decoupling capacitor is arranged between the first interface and the second interface, or is arranged in a vertical projection area of the first interface and the second interface on the interposer layer
Data Source
AI summary
A semiconductor chiplet device includes a package substrate, an interposer layer, a first die and a second die. The first die includes a first interface, and the second die includes a second interface. A first side of the interposer layer is configured to arrange the first die and the second die. The first die and the second die perform a data transmission through the first interface, the interposer layer and the second interface. The package substrate is arranged on a second side of the interposer layer, and includes a decoupling capacitor. The decoupling capacitor is arranged between the first interface and the second interface, or arranged in a vertical projection area of the first interface and the second interface on the package substrate.