Chiplet-First Die Tiling on Stable Carriers for Accurate Placement

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Solution Overview

Problem

Current multi-die electronic packaging architectures face yield issues due to warpage and alignment problems during assembly, particularly with thermal compression bonding (TCB) tools, which limit die placement accuracy and impose stringent warpage limitations, leading to lower yield and additional carrier attachments for mid-level interconnects and package side bumps.

Innovation Solution

The proposed solution involves assembling multi-die packages with first dies placed at initial stages using a die mounter for improved accuracy, attaching a second die with reduced warpage on a dimensionally stable carrier, and forming mid-level interconnects and package side bumps before carrier removal, eliminating the need for additional carriers and minimizing yield losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If thermal compression bonding (TCB) is used to attach advanced node dies to lower node dies at later stages, then integration of different process nodes is enabled, but die placement accuracy is limited by TCB toolset and warpage, leading to lower yield

Engineering Contradiction:

Improveintegration of different process nodesVSAvoiddie placement accuracy

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing die placement on a dimensionally stable carrier at the initial stages of package formation, before warpage occurs. This early placement ensures high accuracy positioning while the carrier maintains its dimensional stability, avoiding the warpage-related precision losses that would occur with later-stage TCB processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a dimensionally stable carrier as an intermediary substrate that enables accurate die placement. This carrier acts as a mediator between the dies and the final package structure, providing a stable platform that is not susceptible to warpage, thereby ensuring high placement accuracy during the assembly process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If TCB attach is performed at later stages of package formation, then advanced node dies can be integrated, but stringent warpage limitations are imposed on the patch and TCB window is significantly reduced

Engineering Contradiction:

Improveadvanced node die integrationVSAvoidTCB window and warpage tolerance

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent performs die attachment at the initial stages of package formation on a dimensionally stable carrier, before warpage develops. This preliminary action allows for a larger TCB window and more relaxed warpage limitations, as the carrier maintains dimensional stability throughout the process, making manufacturing easier and more tolerant of variations.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If a second carrier attach is performed after advanced node dies are attached, then mid-level interconnect and package side bumps can be implemented, but additional yield losses occur

Engineering Contradiction:

Improvemid-level interconnect and package side bump implementationVSAvoidyield

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent merges multiple functions into a single carrier attachment process. By forming mid-level interconnects and package side bumps during the initial carrier attach at the first stage, rather than requiring a second carrier attach later, the process eliminates additional yield losses associated with multiple attachment operations while still achieving the required interconnect functionality.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances die placement accuracy, reduces warpage-related yield losses, and allows for improved thermal management by exposing backside surfaces of dies, thereby improving the overall assembly efficiency and reliability of multi-die packages.

Implementation Method 1

attach a second die with reduced warpage on a dimensionally stable carrier

Methodology Applied

Scientific EffectWarpage reduction: Thermal Expansion

Implementation Method 2

The TCB attach in later stages imposes stringent warpage limitations on the patch and drives a significantly lower TCB window

Methodology Applied

Scientific EffectThermal compression bonding: Compression

Data Source

PatentEP3696852B1Chiplet first architecture for die tiling applications

Publication Date: 2024.01.03 INTEL CORP

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AI summary

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.