Chiplet-in-Cavity Wafer Bonding With Lateral Dielectric Sidewalls
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Solution Overview
Problem
There is a need for an electronic assembly that integrates microelectronic circuits with pre-fabricated interconnects and integrated circuitry, allowing for faster manufacturing and lower costs, particularly for microwave or RF integrated circuits, by decoupling the fabrication of active and passive circuits.
Innovation Solution
A host wafer with pre-fabricated interconnects and integrated circuitry is bonded laterally to chiplets using a dielectric material, where chiplets are embedded in through-wafer cavities, and a backside capping layer improves heat transfer, with interconnects formed directly on the lateral dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microelectronic circuits are fabricated separately and assembled together, then testing of individual circuits is enabled and fabrication yields are improved, but manufacturing time and process complexity increase
Solution Approach 1:
The patent divides the microelectronic circuit into separate functional segments (active circuits on chiplets, passive circuits on host wafer) that can be fabricated, tested, and processed independently before final assembly. This segmentation enables parallel manufacturing workflows where chiplets and host wafers are prepared simultaneously rather than sequentially, reducing total manufacturing time while maintaining the yield benefits of separate fabrication.
Solution Approach 2:
The patent implements preliminary actions by pre-fabricating and pre-testing chiplets and host wafers separately before assembly. The host wafer is prepared with cavity structures and interconnects in advance, and chiplets are fabricated and tested independently. This preliminary preparation enables faster final assembly since all components are ready for integration without requiring post-assembly testing or rework.
2Reliability
If different materials and manufacturing processes are used for separate microelectronic circuits, then circuit performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The host wafer structure serves multiple functions: it provides mechanical support, contains cavities for chiplet integration, provides thermal management pathways, and includes interconnect structures for electrical bonding. This multi-functional design consolidates several required components into a single universal platform, reducing the number of separate manufacturing processes needed while enabling the use of different materials for active and passive circuits.
Solution Approach 2:
The patent introduces an intermediary bonding interface (dielectric material and interconnect structure) that mediates between chiplets fabricated with different materials and processes and the host wafer. This intermediary layer accommodates thermal expansion differences, mechanical property mismatches, and electrical interface variations, allowing diverse circuit technologies to be integrated without requiring complex custom processes for each material combination.
3Device complexity
If active and passive circuits are fabricated together, then manufacturing process is simpler, but manufacturing speed and scalability are reduced
Solution Approach 1:
The patent segments the fabrication process into independent streams: active circuit chiplets are fabricated on separate substrates while passive circuits are fabricated on the host wafer. These parallel fabrication streams can proceed simultaneously using different process optimizations for each circuit type, doubling the effective manufacturing throughput compared to sequential fabrication while maintaining process simplicity within each stream.
4Temperature
If chiplets are integrated into through-wafer cavities using lateral dielectric material bonding, then heat dissipation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The lateral dielectric material bonding structure is designed to be self-aligning, where the dielectric material automatically fills the cavity space and forms bonds with surrounding structures. This self-service bonding mechanism reduces the precision requirements for manual alignment during assembly, as the material flow and curing process naturally accommodate minor dimensional variations while maintaining consistent thermal pathways for heat dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables faster, lower-cost manufacturing of high-performance RF ICs by allowing separate testing of chiplets, reducing manufacturing costs, and improving yield and heat dissipation.
Implementation Method 1
bonded laterally to the sidewalls of the cavity with a dielectric material
Implementation Method 2
a backside capping layer improves heat transfer
Data Source
AI summary
An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.