Chiplet Chunking for Uniform Processing Performance
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Solution Overview
Problem
The manufacturing of large silicon dies for graphics and parallel processors faces challenges such as reduced yields and divergent process technology requirements, along with increased design costs due to the need for high-speed, high-bandwidth interfaces and custom designs for specific market segments.
Innovation Solution
A chiplet architecture that enables late bind SKU fungibility, allowing for a more flexible and nimble product design by using homogenous or heterogeneous chiplets, and a chunking architecture that groups chiplets with uniform execution core counts or power requirements, enabling efficient power delivery and configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large silicon dies are used for graphics and parallel processors, then processing performance is improved, but manufacturing yield is reduced
Solution Approach 1:
The patent divides the large silicon die into multiple smaller chiplet components that can be manufactured separately and then interconnected. This segmentation allows each chiplet to be produced with higher yield while maintaining the overall processing performance through parallel operation of multiple chiplets.
2Power
If large silicon dies are used for graphics and parallel processors, then processing performance is improved, but process technology requirements diverge
Solution Approach 1:
By segmenting the processor into separate chiplets, each chiplet can be manufactured using standardized process technologies. This reduces the divergence of process technology requirements compared to manufacturing a single large die with multiple divergent components.
Solution Approach 2:
The chiplet architecture creates universal building blocks that can be used across different processor configurations and market segments. The same chiplet designs can be reused in various combinations, reducing the need for custom designs and simplifying process technology requirements.
3Adaptability or versatility
If custom designs are created for specific market segments, then market specificity is improved, but design costs increase
Solution Approach 1:
The patent employs universal chiplet designs that can be configured in different combinations to serve various market segments. This reusability significantly reduces design costs compared to creating custom designs for each market segment, while still maintaining the ability to address specific market requirements through configuration.
Solution Approach 2:
The chiplet architecture enables dynamic configuration of processor specifications through different chiplet combinations. This allows a single set of standardized chiplet designs to adapt to various market segments without requiring custom design work, thereby reducing design costs while maintaining market specificity.
Data Source
AI summary
Described herein is a modular parallel processor and associated manufacturing method in which the parallel processor is assembled from multiple chiplets that populate multiple chiplet slots of an active base chiplet die. The multiple chiplets are tested to determine characteristics of the chiplet, such as a number of functional units or a power consumption metric for the chiplet. The multiple chiplet slots can be configured to be populated by one or more chunks of multiple chiplets, where each chunk has a pre-determined collective value. The pre-determined collective value can be a total number of functional execution cores within a chunk or a collective power metric for the chunk.