Chiplet Debug Routing Over Inter-Chiplet Links
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Solution Overview
Problem
Conventional chip debugging methods using a JTAG daisy chain are limited by signal integrity issues, scalability, and increased complexity and cost due to long chains and dedicated wiring, which are exacerbated by single points of failure.
Innovation Solution
A chiplet architecture with inter-chiplet interconnect interfaces, selection modules, and processing modules that facilitate direct communication and information forwarding between chiplets, eliminating the need for a JTAG daisy chain and reducing reliance on additional wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a JTAG daisy chain is used to debug multiple chips, then all chips can be debugged through a single interface, but the chain length is limited by signal integrity and scalability
Solution Approach 1:
The system segments the debugging function by introducing intermediate processing modules in each chip that can independently handle and forward debugging information. This breaks the long daisy chain into shorter segments, improving signal integrity while maintaining the ability to debug multiple chips through a single external interface.
Solution Approach 2:
Processing modules within each chip act as intermediaries that receive debugging information from the daisy chain, process it locally, and forward it to the next chip. This intermediary function reduces signal degradation by limiting the length of direct connections while enabling multi-chip debugging.
2Ease of operation
If a JTAG daisy chain connects multiple chips, then debugging can be performed through one interface, but additional wiring is needed to ensure correct signal paths
Solution Approach 1:
The inter-chip interconnect interfaces are designed to serve dual purposes: normal data communication between chips and debugging information transmission. This eliminates the need for separate dedicated wiring for debugging, as the existing interconnect infrastructure is reused for both functions.
Solution Approach 2:
The debugging pathway is merged with the normal data communication pathways by using the same inter-chip interconnect interfaces for both purposes. This consolidation reduces PCB wiring complexity while maintaining ease of debugging operation.
3Device complexity
If a single JTAG interface is used for all chips, then interface complexity is reduced, but a single point of failure affects all chips
Solution Approach 1:
The debugging function is segmented across multiple independent processing modules, each capable of handling debugging information for its associated chip. This segmentation creates redundancy, so that a failure in one module does not affect debugging of other chips, while still allowing access through a single external interface.
Solution Approach 2:
Each chip is equipped with local processing capability that can independently handle debugging information. This local quality ensures that debugging operations can continue for unaffected chips even when one chip or interface fails, improving overall system reliability.
Data Source
AI summary
The present disclosure provides a chiplet, including: an inter-chiplet interconnect interface connected to one other chiplet, a selection module, and a processing module; the inter-chiplet interconnect interface receives second debugging information from the other chiplet; the selection module receives at least one piece of debugging information of the second debugging information, and send the at least one piece of debugging information to the processing module; and the processing module forwards, if the at least one piece of debugging information is debugging information for debugging of the chiplet, the at least one piece of debugging information within the chiplet for the debugging of the chiplet, and sends, if the at least one piece of debugging information is debugging information for debugging of the other chiplet, the at least one piece of debugging information to the inter-chiplet interconnect interface.