Chiplet Debug Architecture for Cross-Vendor Test Interoperability

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Solution Overview

Problem

The integration of chiplets in integrated circuits faces challenges in seamless testing and debugging due to diverse architectures, interfaces, and power requirements, limiting compatibility and interoperability between chiplets from different manufacturers.

Innovation Solution

A unified test and debug architecture is implemented using an external hardware debug interface that supports interface-agnostic debug messages, such as UCIe™ packets, allowing for interoperable debug/test solutions across various chiplet configurations, with debug nodes and endpoints that facilitate communication and routing within and between chiplets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If chiplets from different manufacturers are integrated into a single package, then functionality and scalability are improved, but compatibility and interoperability issues arise due to diverse architectures, interfaces, and power requirements

Engineering Contradiction:

Improvefunctionality and scalabilityVSAvoidcompatibility and interoperability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a universal test and debug architecture that provides a common interface and protocol layer across diverse chiplet architectures. This universal layer enables single test equipment to interact with multiple chiplet types through standardized commands, achieving multi-functionality that resolves compatibility issues while maintaining the ability to test heterogeneous chiplet combinations

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If traditional monolithic chips are used, then manufacturing simplicity is maintained, but flexibility and cost efficiency are limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidflexibility and cost efficiency

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent adopts chiplet segmentation where large monolithic chips are divided into smaller, independent functional units. Each chiplet can be manufactured separately using optimal fabrication processes for its specific function, then integrated into a package. This segmentation enables manufacturing simplicity at the chiplet level while achieving flexibility and cost efficiency through modular assembly and selective integration

Inventive Principle:

Principle #1Segmentation

3Reliability

If chiplets are tested at multiple stages from sort stage to system level, then testing completeness is improved, but test complexity and time increase

Engineering Contradiction:

Improvetesting completenessVSAvoidtest time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary testing at the sort stage using a universal test architecture that performs initial validation of chiplet functionality before integration. This preliminary action identifies defective chiplets early, preventing them from progressing to more complex and time-consuming system-level tests, thereby reducing overall test time while maintaining testing completeness

Inventive Principle:

Principle #10Preliminary action

4Difficulty of detecting and measuring

If diverse debug interfaces are used for different chiplet architectures, then architecture-specific debugging capability is improved, but interoperability and ease of operation decrease

Engineering Contradiction:

Improvedebugging capabilityVSAvoidinteroperability

Core Design Contradiction:

Difficulty of detecting and measuringVSEase of operation

Solution Approach 1:

The patent introduces an intermediary universal debug interface layer that sits between the test equipment and diverse chiplet architectures. This intermediary translates standardized debug commands into architecture-specific operations, enabling single debug equipment to interact with multiple chiplet types through a common interface, thereby improving interoperability without sacrificing architecture-specific debugging capability

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12578384B2Unified test and debug chiplet architecture

Publication Date: 2026.03.17 INTEL CORP

AI summary

Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.