Chiplet Edge Interconnect Structure for Direct Die Stacking
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Solution Overview
Problem
As the semiconductor industry continues to increase integration density, connecting integrated circuit dies through interposers alone becomes challenging due to the need for more complex and dense interconnects.
Innovation Solution
The implementation of edge interconnect features on integrated circuit dies, which extend from the circuit region through the seal region into the scribe line, allowing for direct connection between dies without the need for interposers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used to connect integrated circuit dies, then signal transfer between dies is enabled, but the complexity and cost of interconnects increases
Solution Approach 1:
The patent extracts the interconnect function from the separate interposer substrate and integrates it directly into the integrated circuit die itself. Edge interconnect features are formed extending from the circuit region through the seal region into the scribe line, eliminating the need for external interposer interconnects and reducing overall system complexity.
Solution Approach 2:
The patent merges the interconnect functionality with the integrated circuit die by forming edge interconnect features that extend from the circuit region through the seal region. This combines the die and interconnect into a single integrated structure, eliminating the separate interposer component.
2Productivity
If integration density increases, then more functions are integrated into a given area, but connecting dies through interposers becomes more challenging
Solution Approach 1:
The patent utilizes the edge/dimension along the periphery of the die by forming interconnect features that extend into the scribe line region. This edge-based approach provides additional interconnect capacity without consuming valuable core circuit area, enabling higher integration density.
Solution Approach 2:
The patent segments the interconnect function into distributed edge interconnect features along the periphery of the die, rather than relying on centralized interposer connections. This segmentation enables more flexible and dense routing capabilities.
3Ease of manufacture
If edge interconnect features extend into the scribe line, then direct connection between dies is enabled, but the seal region must be traversed
Solution Approach 1:
The patent performs preliminary action by forming the edge interconnect features to extend through the seal region during the die fabrication process, before die attachment. This preliminary extension through the seal region simplifies subsequent die-joining operations and enables direct connections.
Data Source
AI summary
Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.