Fanout Interposer Chiplet Layout Without TSV Package Routing
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in integrating multiple components within smaller spaces while maintaining high input/output density and performance, particularly in portable and mobile electronic devices.
Innovation Solution
The integration of an interposer chiplet within a semiconductor package, which provides fine routing between components, along with a redistribution layer (RDL) that spans over the encapsulation layer, allowing for electrical connections between components and reducing the need for through silicon vias (TSVs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are used for interconnection, then vertical electrical connection is achieved, but packaging complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the TSV formation process from the package structure by using an interposer chiplet that provides routing pathways without requiring TSVs. The interposer chiplet takes out the need for vertical vias through alternative routing paths on the chiplet surface and within its substrate, thereby reducing packaging complexity while maintaining electrical connection reliability.
Solution Approach 2:
The interposer chiplet acts as an intermediary between the first and second components, providing fine routing pathways that eliminate the need for direct TSV connections. This mediator approach allows electrical signals to route through the interposer chiplet's conductive pathways rather than requiring complex TSV structures, reducing overall packaging complexity.
2Quantity of substance
If multiple components are integrated within smaller spaces, then device density increases, but routing complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the packaging system into distinct functional modules: first component, second component, and interposer chiplet with embedded conductive pillars. This segmentation allows each component to be manufactured and tested separately, then integrated together, thereby reducing overall manufacturing difficulty while achieving high component density through systematic arrangement.
Solution Approach 2:
The patent transitions from planar routing to three-dimensional routing by embedding conductive pillars vertically within the interposer chiplet and using stacked configurations. This dimensional change enables fine pitch routing in the vertical dimension, allowing multiple components to be integrated in smaller spaces without proportionally increasing routing complexity.
3Productivity
If fine pitch component-to-component routing is implemented, then interconnection efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The conductive pillars are embedded within the interposer chiplet during its fabrication process, before the final package assembly. This preliminary action establishes the fine pitch routing pathways in advance with precise positioning, eliminating the need for high-precision alignment during subsequent assembly steps, thereby reducing manufacturing precision requirements while maintaining interconnection efficiency.
Data Source
AI summary
Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.