Chiplet-First Die Tiling Assembly for Warpage-Limited Packaging
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Solution Overview
Problem
Current multi-die electronic packaging architectures face yield issues due to warpage and alignment problems during assembly, particularly with thermal compression bonding (TCB) tools, which limit die placement accuracy and impose stringent warpage limitations, leading to additional yield losses.
Innovation Solution
The proposed solution involves assembling multi-die packages with first dies placed early in the process using a die mounter for improved accuracy, attaching a second die with reduced warpage on a dimensionally stable carrier, and forming mid-level interconnects and Package Side Bumps before carrier removal, eliminating the need for additional carriers and minimizing yield losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If thermal compression bonding (TCB) is used to attach advanced node dies to lower node dies, then integration of different process nodes is enabled, but die placement accuracy is limited by TCB toolset and warpage
Solution Approach 1:
The patent attaches the advanced node die to the lower node die at an early stage in the package formation process, before the patch is attached to the carrier. This preliminary attachment allows for better alignment and placement accuracy because the structures are smaller and more manageable at this stage, avoiding the warpage and alignment issues that occur with later-stage TCB operations on fully assembled patches.
2Adaptability or versatility
If TCB attach is performed at later stages of package formation, then advanced node dies can be integrated, but stringent warpage limitations are imposed and TCB window is reduced
Solution Approach 1:
The advanced node die is attached to the lower node die before the patch assembly is completed and mounted to the carrier. This early attachment occurs when the structures involved are smaller and experience minimal warpage, providing a larger process window and higher reliability for the TCB operation.
3Adaptability or versatility
If a second carrier attach is performed after advanced node dies are attached, then mid-level interconnect and Package Side Bumps can be implemented, but additional yield losses occur
Solution Approach 1:
The patent combines multiple operations into a single carrier attach process. The advanced node die is attached to the lower node die, and the patch is attached to the carrier in one integrated sequence, eliminating the need for a separate second carrier attach operation. This reduction in process steps directly reduces yield losses while still enabling mid-level interconnect and Package Side Bump implementation.
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.