Chiplet Package Floorplan With Hierarchical Bump Pattern Reuse
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Solution Overview
Problem
The process of designing a floorplan specifying the bumps of a package die in integrated circuit (IC) design requires manual placement by senior engineers, consuming over 100 hours of labor, and lacks automation in existing electronic design automation (EDA) tools.
Innovation Solution
The integration of three-dimensional Integrated circuit (3DIC) design with chiplet and package design through automated floorplan and bump modeling, which defines boundary conditions, imports tile outlines, and automatically fills slave cells with a bump pattern matching the master cell, generating a floorplan and bump placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual placement of bumps is performed by senior engineers, then placement accuracy and design quality are maintained, but labor time and cost increase significantly (over 100 hours)
Solution Approach 1:
The patent applies copying by creating a master cell containing the bump pattern that is then automatically replicated to slave cells through hierarchical floorplan generation. This allows the bump placement design to be copied systematically across the entire package die, maintaining consistency and accuracy while eliminating manual repetition.
Solution Approach 2:
The patent segments the floorplan into hierarchical cells (master cells and slave cells), each containing specific bump patterns. This segmentation allows the complex bump placement task to be divided into manageable units that can be independently defined and then automatically assembled, reducing the overall design time while maintaining precision.
2Productivity
If automated floorplan generation is implemented, then design time is reduced significantly, but automation capability must be developed from scratch in existing EDA tools
Solution Approach 1:
The patent introduces a hierarchical dimension to the floorplan structure, organizing bumps and cells into multiple levels (master cells containing slave cells). This hierarchical approach adds a structural dimension that enables automated generation while managing complexity through organized abstraction levels.
Solution Approach 2:
The patent creates a universal master cell template that can serve multiple slave cells across different regions of the package die. This multi-functional approach allows a single bump pattern design to be reused systematically, reducing the need for separate automated tools for each region while maintaining productivity.
Data Source
AI summary
The disclosed computer-implemented method can include defining, by at least one processor, one or more boundary conditions. The method can additionally include importing, by the at least one processor, one or more tiles outlines that at least define importing, by the at least one processor, one or more tiles outlines that at least define a cell hierarchy for one or more chiplets. The method can also include defining, by the at least one processor and based at least in part on the one or more tiles outlines, one or more cells of the one or more chiplets at least in part by automatically filling one or more slave cells of the one or more chiplet with a same bump pattern as a master cell of the one or more chiplets. The method can further include generating, by the at least one processor and based at least in part on the defined boundary conditions and the defined one or more cells, a floorplan and bump placement for a package design. Various other methods, systems, and computer-readable media are also disclosed.