Chiplet Floorplan Optimization for Yield and Wafer Throughput

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Solution Overview

Problem

Existing semiconductor design methods struggle to optimize chiplet size and placement in advanced packaging solutions, leading to inefficiencies in performance, power consumption, and cost, particularly in 2.5D and 3D architectures, due to the complexity of balancing competing variables such as performance, power efficiency, manufacturing yield, and cost.

Innovation Solution

A chiplet optimization tool kit utilizing AI/ML models and ECAD tools to determine optimal chiplet size and placement, considering parameters like die reticle size, chip module size, and gross modules per wafer, leveraging AMD design rules and proprietary data to streamline the floorplan optimization process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional semiconductor design methods are used for chiplet layout, then design simplicity is maintained, but manufacturing yield and cost efficiency deteriorate due to inability to optimize competing variables

Engineering Contradiction:

Improvemanufacturing yieldVSAvoiddesign complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The optimization process is segmented into distinct modules: chiplet size optimization, placement optimization, and floorplan generation. Each module handles specific parameters independently, allowing complex multi-variable optimization to be broken down into manageable segments that can be processed systematically

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An automated optimization tool acts as an intermediary between design requirements and manufacturing outcomes. This tool incorporates manufacturing constraints and optimization algorithms to bridge the gap between design simplicity and manufacturing precision, eliminating the need for manual iteration while maintaining design accessibility

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If chiplet size and placement are not optimized, then design process is simpler, but mask field utilization and gross modules per wafer deteriorate

Engineering Contradiction:

Improvegross modules per waferVSAvoidoptimization process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Chiplet size and placement are optimized in advance during the design phase using automated algorithms. This preliminary optimization ensures that mask field utilization and gross modules per wafer are maximized before manufacturing begins, eliminating the need for post-manufacturing adjustments and improving overall productivity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system automatically adjusts chiplet size parameters and placement coordinates to optimize mask field utilization. By dynamically changing these parameters through algorithms, the system achieves higher gross modules per wafer without requiring manual intervention or complex design processes

Inventive Principle:

Principle #35Parameter changes

3Loss of time

If manual chiplet layout methods are used, then tool complexity is reduced, but time-to-market and development costs increase

Engineering Contradiction:

Improvetime-to-marketVSAvoidtoolkit complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Manual iterative layout adjustment is replaced with automated computational algorithms. The optimization toolkit uses software-based algorithms to automatically determine optimal chiplet configurations, eliminating the time-consuming manual process while managing complexity through automated tooling

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The optimization toolkit performs self-service by automatically optimizing chiplet layouts without requiring extensive manual intervention. The system independently processes design inputs, applies optimization algorithms, and generates optimized floorplans, reducing both time-to-market and reliance on expert manual analysis

Inventive Principle:

Principle #25Self-service

4Adaptability or versatility

If advanced packaging techniques are implemented without optimization, then integration capability is improved, but thermal management and power efficiency worsen

Engineering Contradiction:

Improveintegration capabilityVSAvoidthermal management

Core Design Contradiction:

Adaptability or versatilityVSTemperature

Solution Approach 1:

The optimization process considers local thermal characteristics when determining chiplet placement. High-power chiplets are strategically positioned in areas with better thermal dissipation capabilities, while low-power chiplets are placed in thermally sensitive regions. This localized optimization ensures that integration capability is maximized while thermal management requirements are met through spatial distribution

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20260073104A1Chiplet optimization tool kit

Publication Date: 2026.03.12 ADVANCED MICRO DEVICES INC

AI summary

Embodiments herein describe a method including receiving an initial chiplet layout, determining chiplet size for improving mask field utilization (MFU) using a plurality of first parameters, determining chiplet placement for improving gross modules per wafer (GMPW) using a plurality of second parameters, and generating an updated chiplet floorplan based on the determined chiplet size and the determined chiplet placement. Machine learning (ML) models are used to generate the optimized updated chiplet floorplan.