Chiplet Gearbox Serialization for Lower-Cost MCM Packaging

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Solution Overview

Problem

Chiplet-based architectures for multi-chip modules (MCMs) face increased costs due to expensive packaging components and processes, particularly with high-density micro-bump technology, which affects yield and signal integrity for larger integrated circuit chips.

Innovation Solution

A multi-chip module (MCM) design that employs a gearbox chiplet to reduce the number of interface bumps by omitting a subset of signals, serializing, and then recreating them, allowing for the use of larger, less expensive bumps and efficient error coding techniques like forward error correction (FEC) to maintain signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-density micro-bump technology is used for chiplet packaging, then signal integrity and bandwidth are improved, but manufacturing cost and complexity increase

Engineering Contradiction:

Improvesignal integrityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The interface signals are segmented into two groups: frequently accessed signals that maintain direct point-to-point connections, and less frequently accessed signals that are multiplexed. This segmentation allows the use of fewer, larger bumps for the multiplexed connections while maintaining signal integrity for critical paths.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple interface signals are merged into a single serialized data stream that travels through a reduced number of physical channels. The gearbox chiplet combines multiple signal lines into fewer high-speed serial links, reducing the total number of bumps required while maintaining equivalent bandwidth through time-division multiplexing.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If high-density micro-bump technology is used for chiplet packaging, then bandwidth capability is improved, but device complexity increases

Engineering Contradiction:

Improvebandwidth capabilityVSAvoidpackaging complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The gearbox chiplet acts as an intermediary device between the memory chiplet and the logic chiplet. It performs signal serialization, multiplexing, and protocol conversion, simplifying the packaging architecture by replacing complex parallel micro-bump interconnections with fewer serialized high-speed links.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The interface parameters are changed from parallel signaling with many low-speed channels to serialized signaling with fewer high-speed channels. This parameter change reduces the number of physical interconnections required while maintaining or increasing the overall bandwidth capability through higher per-channel data rates.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If fewer interface bumps are used, then manufacturing cost decreases, but signal integrity may deteriorate

Engineering Contradiction:

Improvemanufacturing costVSAvoidsignal integrity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The physical mechanical interconnection system (multiple parallel micro-bumps) is replaced with an electrical signaling system (serialized high-speed links with error correction). Instead of relying on the physical proximity and density of bumps for signal integrity, the system uses electrical protocols including encoding, error detection, and correction to maintain reliability with fewer physical connections.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11841815B1Chiplet gearbox for low-cost multi-chip module applications

Publication Date: 2023.12.12 ELIYAN CORP

AI summary

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first full set of signals associated with the first interface and to omit a subset of the full set of signals to generate a reduced set of signals. Serialization circuitry serializes the reduced set of signals to generate a serialized set of signals. A second interface transmits the serialized set of signals with a second number of interface contacts that is less than the first number of interface contacts. A logic IC chip includes a third interface coupled to the second interface via a set of links and configured to match the second interface. Deserialization circuitry deserializes the serialized set of signals. Reconversion circuitry recreates signals corresponding to the omitted subset of the full set of signals and aggregates the recreated signals with the deserialized signals to form a second full set of signals that correspond to the first full set of signals.