Chiplet Hub DMA Architecture for Non-Host Request Handling
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Solution Overview
Problem
Chiplet-based systems are limited to a few large manufacturers due to proprietary interconnections, preventing small to medium entities from realizing the performance and cost benefits of chiplet technology, and existing SoCs face yield and optimization issues with complex designs.
Innovation Solution
A chiplet hub architecture that integrates multiple specialized chiplets with a DMA controller, enabling flexible interconnects and shared resources, allowing for scalable and efficient system integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If proprietary chiplet interconnections are used, then manufacturing control and performance optimization are improved, but device complexity and development cost increase significantly
Solution Approach 1:
The patent implements a universal interconnection protocol that enables different chiplet types (accelerators, memory, I/O) to communicate through a standardized interface. The hub architecture provides multi-functional connectivity, allowing the same interconnection fabric to handle various data types and communication patterns without requiring proprietary specialized links for each chiplet type.
Solution Approach 2:
The system divides the complex interconnection functionality into separate modular components: the hub provides routing and protocol management, while individual chiplets provide specialized functions. This segmentation allows each component to be optimized independently while maintaining overall system compatibility through standard interfaces.
2Adaptability or versatility
If more semiconductor functions are integrated into a single SoC, then system integration is improved, but yield decreases and production cost increases
Solution Approach 1:
The patent divides the system into multiple independent chiplets that can be manufactured separately using optimized processes for each function. Each chiplet has a smaller die size suitable for its specific function, improving yield. The hub interconnects these chiplets after manufacturing, achieving high-level integration without the risks of monolithic SoC fabrication.
Solution Approach 2:
Each chiplet is manufactured with local quality optimization - using semiconductor processes specifically tuned for that chiplet's function (e.g., different transistor geometries, materials, or process nodes). This allows each component to achieve peak performance and yield for its specific purpose while the overall system maintains high integration through the hub interconnect.
3Speed
If DMA channels are allocated exclusively to host devices, then host performance is improved, but non-host device functionality and system versatility are limited
Solution Approach 1:
The patent implements dynamic DMA channel allocation where channels can be assigned to different devices based on current system needs. The hub controller can allocate DMA resources to non-host devices when the host is not actively using them, and switch allocations dynamically. This dynamic sharing maintains high host performance while enabling versatile support for accelerators, memory devices, and other non-host components.
Solution Approach 2:
Non-host devices are enabled to initiate and manage their own DMA operations directly through the hub, without requiring constant host intervention. The hub provides self-service capabilities where accelerators and memory devices can autonomously perform data transfers, reducing host overhead and improving overall system versatility while maintaining efficient resource utilization.
Data Source
AI summary
A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.