Chiplet Hub Fabric with Isolated Links for Scalable Integration
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Solution Overview
Problem
The limitations of chiplet-based systems are primarily due to proprietary interconnections, which restrict development to a few large manufacturers, preventing small to medium entities from realizing the performance and cost benefits of chiplet technology.
Innovation Solution
A chiplet hub architecture that utilizes a central fabric for interconnects, allowing multiple chiplet types with isolated interconnects, including a hub manager for management and a HDMA controller for efficient data transfer, enabling flexible and scalable integration of chiplets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If proprietary chiplet interconnections are used, then manufacturing control and performance optimization are improved, but accessibility and adoption by small to medium entities deteriorate
Solution Approach 1:
The patent segments the chiplet interconnection system into standardized interface components that can be independently designed and manufactured. The chiplet hub architecture divides the complex interconnection task into manageable modules including PHY layers, link layers, and management layers, allowing different entities to contribute specialized chiplets while maintaining system-wide compatibility through standardized interfaces.
Solution Approach 2:
The patent creates a universal chiplet hub architecture that can accommodate multiple types of chiplets from different manufacturers through standardized interconnection protocols. The hub manager and DMA controllers provide multi-functional capabilities that work with various chiplet types, enabling both large and small entities to participate in the ecosystem while maintaining optimized performance through standardized interfaces.
2Adaptability or versatility
If multiple specialized chiplets are integrated, then system performance and functionality are improved, but system complexity and integration difficulty increase
Solution Approach 1:
The patent introduces a chiplet hub as an intermediary component that manages communications and data transfers between multiple specialized chiplets. The hub manager and DMA controllers act as mediators that handle the complexity of integration, allowing specialized chiplets to be combined without requiring direct complex interconnections between each pair of chiplets. This intermediary layer simplifies the integration process while enabling high functionality.
3Speed
If data transfer efficiency is improved through direct chiplet connections, then communication speed increases, but isolation and security between different chiplet functions decrease
Solution Approach 1:
The patent implements local quality by providing isolated interconnection paths for different chiplet functions through the chiplet hub. Each chiplet type can have dedicated DMA controllers and data transfer paths that maintain high speed communication while being logically isolated from other chiplet functions. The hub manager controls access to these paths, ensuring security and isolation while maintaining performance through optimized local connections.
Data Source
AI summary
A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.