Chiplet Hub Architecture for Shared HBM and Isolated System Instances
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Solution Overview
Problem
Chiplet-based systems are limited to a few large manufacturers due to proprietary interconnections, preventing small to medium entities from realizing the performance and cost advantages of chiplet technology, and existing SoCs face yield and optimization issues with complex designs.
Innovation Solution
A chiplet hub architecture that uses a centralized hub manager to interconnect specialized chiplets, including an HDMA controller, hub manager, and high-bandwidth memory, enabling flexible and efficient communication among various chiplets and memories, and supports multiple semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If proprietary chiplet interconnections are used, then interconnection functionality is achieved, but access to chiplet technology is limited to a few large manufacturers
Solution Approach 1:
The patent introduces a standardized hub architecture as an intermediary component that mediates between chiplets and the external world. This hub provides a common interface and control mechanism that simplifies access to chiplet-based systems, allowing smaller manufacturers to adopt the technology without developing proprietary interconnection solutions. The hub acts as a mediator that abstracts the complexity of chiplet interconnections behind a standardized interface.
2Adaptability or versatility
If a large, complex SoC is designed to integrate multiple functions, then system functionality is achieved, but yield decreases and production costs increase
Solution Approach 1:
The patent divides the monolithic SoC into separate, smaller chiplets that can be manufactured independently using optimized processes for each function. This segmentation allows each chiplet to be produced with higher yield on smaller dies, while the standardized hub enables these separate chiplets to function together as an integrated system. The segmentation principle directly addresses the yield problem by avoiding the need to manufacture large, complex monolithic devices.
Solution Approach 2:
The standardized hub architecture provides universal functionality that can work with multiple types of chiplets and memory devices. This multi-functional hub can interface with different chiplet types (compute, graphics, AI, etc.) and various memory technologies (HBM, GDDR, LPDDR), allowing the same hub design to support diverse system configurations without requiring custom interconnection designs for each application.
3Speed
If a monolithic device is used to achieve high performance, then performance is improved, but production costs increase due to lower yield
Solution Approach 1:
By segmenting the monolithic device into smaller chiplets, each manufactured on optimized process nodes, the overall system performance is maintained through parallel processing and high-speed interconnections via the standardized hub, while manufacturing yield and cost-effectiveness are improved through smaller, more manufacturable die sizes.
Solution Approach 2:
The patent changes the manufacturing parameters by moving from large-die monolithic fabrication to smaller-die chiplet fabrication using different, optimized process parameters for each chiplet type. This allows each chiplet to be manufactured at optimal process conditions, improving both yield and performance while reducing costs.
Data Source
AI summary
A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.