Chiplet Hub With Stacked HBM for Scalable Memory Access
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Solution Overview
Problem
Chiplet-based systems are limited to a few large manufacturers due to proprietary interconnections, preventing small to medium entities from realizing the performance and cost benefits of chiplet technology, and SoCs face yield and optimization issues with complex designs.
Innovation Solution
A chiplet hub architecture that integrates multiple specialized chiplets with a central fabric for interconnectivity, utilizing a hub manager and HDMA controller to manage memory and device communications, enabling flexible and efficient interconnections among chiplets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If proprietary chiplet interconnections are used, then manufacturing precision and reliability are improved, but device complexity and ease of manufacture deteriorate due to limited accessibility
Solution Approach 1:
The patent segments the chiplet interconnection system into standardized interface modules that can be independently manufactured and assembled. The chiplet hub architecture divides the complex interconnection task into manageable components including memory interfaces, I/O interfaces, and compute interfaces, allowing different entities to manufacture specialized chiplets that interconnect through standardized protocols.
Solution Approach 2:
The patent creates universal interconnection interfaces that can serve multiple functions and connect different types of chiplets. The standardized protocols and interface definitions allow the same interconnection infrastructure to support various chiplet types from different manufacturers, achieving both reliability through standardization and ease of manufacture through broad accessibility.
2Adaptability or versatility
If monolithic SoC design is used, then device integration is improved, but manufacturing precision deteriorates due to yield issues with large die sizes
Solution Approach 1:
The patent divides the monolithic SoC into multiple smaller chiplets that can be manufactured separately on smaller dies, improving yield. Each chiplet can be optimized for its specific function while maintaining overall system integration through the standardized interconnection interfaces. This segmentation allows high-performance integration without the yield penalties of large monolithic dies.
3Productivity
If specialized semiconductor processes are used for different functions, then performance is improved, but device complexity increases due to multiple chips required
Solution Approach 1:
The patent introduces standardized interconnection interfaces as intermediaries between specialized chiplets from different semiconductor processes. These interfaces act as mediators that translate between different chiplet types, allowing high-performance specialized processors to work together without requiring a single complex multi-process fabrication facility. The hub manager coordinates these interactions, simplifying the overall system complexity.
4Productivity
If large die sizes are used for high transistor counts, then computing performance is improved, but manufacturing precision deteriorates due to yield problems
Solution Approach 1:
The patent segments the large die into multiple smaller chiplets, each with fewer transistors that can be manufactured with higher yield. The computing performance is maintained by parallelizing work across multiple chiplets that interconnect through standardized interfaces. This approach achieves the same computational throughput as a large monolithic die while benefiting from improved manufacturing yield on smaller dies.
Data Source
AI summary
A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.