Resilient Chiplet Interconnects With Redundancy and ECC

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Solution Overview

Problem

Existing integrated circuit (IC) chiplet interconnects in 3D packages face challenges with high-speed and reliable connectivity, particularly due to faults that are not adequately addressed by current fault-tolerant mechanisms.

Innovation Solution

Implementing a dual-layer protection mechanism comprising redundant interconnects and error correction codes (ECC) to replace faulty interconnects, with spatial redundancy at the unit level and ECC groups to enhance fault tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant interconnects are implemented to replace faulty units, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvefault toleranceVSAvoidinterconnect structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The interconnect structure is segmented into functional units, each containing multiple interconnects that can be independently controlled. This segmentation allows selective activation of redundant interconnects within specific units without affecting the entire system, thereby managing complexity while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Redundant interconnects are pre-configured and prepared in advance within each functional unit. When a fault is detected, the system can immediately switch to the pre-prepared redundant interconnects without requiring complex real-time decision-making or system-wide reconfiguration, thus improving reliability while controlling complexity.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If spatial redundancy at unit level is implemented, then fault tolerance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvefault toleranceVSAvoidmanufacturing process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The redundant interconnects are designed with the same structure and functionality as the primary interconnects, allowing them to be manufactured using identical processes. This universality simplifies manufacturing by eliminating the need for specialized fabrication steps for redundant components, while still providing the required fault tolerance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If ECC groups are implemented to correct errors, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveerror correctionVSAvoidcontrol circuitry

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The error correction code (ECC) functionality is merged with the existing interconnect control logic. The control circuitry that manages the selection and activation of redundant interconnects is combined with the ECC encoding and decoding functions, creating a unified control mechanism that reduces overall system complexity while maintaining error correction capabilities.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250209027A1Resilient I/O interconnect

Publication Date: 2025.06.26 INTEL CORP

AI summary

Disclosed are interconnect systems with spatially separated redundant interconnects to replace faulty interconnects. In some embodiments, error correction code techniques may also be used to enhance communications robustness.