Chiplet Interface Retransmission Control for Error Correction

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Solution Overview

Problem

Chiplet architectures face challenges in managing high bit error rates in chip-to-chip communications due to the complexity of interconnects, which traditional error correction mechanisms like SEC-DED and CRC-based methods are inadequate in correcting errors without requiring retransmissions.

Innovation Solution

A retry-based error correction mechanism is implemented using Type-0 and Type-1 Flits, where Type-0 Flits carry data and Type-1 Flits provide control signals for error correction, allowing for efficient retransmission management to maintain low bit-error-rates in chip-to-chip interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction mechanisms (SEC-DED, CRC-based methods) are used in chiplet architectures, then error detection capability is provided, but retransmissions are required which increase latency and reduce communication efficiency

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcommunication latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and attaching syndrome bits to data packets during transmission. These syndrome bits contain error correction information that enables the receiving chiplet to immediately identify and correct errors without requiring retransmission, thus resolving the contradiction between reliability and latency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces syndrome bits as an intermediary element that carries error correction information alongside data packets. These syndrome bits act as a mediator that enables direct error correction at the receiver, eliminating the need for retransmission protocols and reducing communication latency while maintaining high reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If complex interconnect mechanisms are implemented to achieve high bandwidth and low latency, then communication performance is improved, but bit error rates increase due to signal integrity issues

Engineering Contradiction:

Improvecommunication bandwidthVSAvoidbit error rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-computing syndrome bits that encode error detection and correction information before transmission. This allows the receiving chiplet to immediately correct errors caused by high-speed interconnect signal integrity issues without stopping communication, thus maintaining both high bandwidth and low error rates

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through syndrome bits that provide real-time error information about transmitted data. This feedback mechanism enables the receiving chiplet to identify and correct errors caused by high-speed communication challenges, maintaining reliability without sacrificing the high bandwidth performance of complex interconnects

Inventive Principle:

Principle #23Feedback

3Reliability

If additional control signals are added to manage error correction, then error handling reliability is improved, but device complexity and overhead increase

Engineering Contradiction:

Improveerror handling capabilityVSAvoidcontrol signal overhead

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges error correction information with data packets by attaching syndrome bits directly to the data being transmitted. This combination eliminates the need for separate control signals and dedicated error management channels, reducing device complexity and control overhead while maintaining robust error handling capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent applies universality by designing syndrome bits that serve multiple functions: error detection, error correction, and communication status indication. This multi-functionality reduces the need for additional specialized control signals, thereby reducing overall device complexity while improving error handling reliability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260088927A1System-level techniques for error correction in chip-to-chip interfaces

Publication Date: 2026.03.26 XILINX INC

AI summary

Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.