Bond-to-Bond Chiplet Interface With Always-On Wake Signaling
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Solution Overview
Problem
Designing a scalable and efficient interface for coupling multiple chiplet ICs in computer systems poses challenges due to limited space, latency, and power management issues, especially when heterogeneous chiplets are involved, requiring a flexible and low-latency bond-to-bond interface.
Innovation Solution
Implementing a bond-to-bond interface with always-on and power-managed portions that allow chiplets to communicate efficiently, even when one chiplet is in a reduced power state, by using wake-up signals through always-on portions to activate power-managed circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chiplets are coupled through traces on a circuit board, then ease of manufacture is improved, but speed deteriorates due to increased latency
Solution Approach 1:
The interface is segmented into always-on and power-managed portions, allowing critical communication paths to remain active while other portions can be powered down. This segmentation enables direct bonding of chiplets without requiring full circuit board traces for all connections.
Solution Approach 2:
The always-on portion acts as an intermediary that remains active to facilitate wake-up signals and maintain communication readiness, enabling faster inter-chiplet communication compared to full circuit board traces while managing power consumption.
2Use of energy by moving object
If chiplets are placed in reduced power state, then use of energy is improved, but speed deteriorates due to wake-up latency
Solution Approach 1:
The interface circuit is divided into always-on and power-managed portions. The always-on portion consumes minimal power to maintain communication readiness and send wake-up signals, while the power-managed portion can be fully powered down when not in use, achieving both power savings and fast wake-up.
Solution Approach 2:
The always-on portion performs preliminary actions by maintaining readiness to send wake-up signals before the power-managed portion needs to be activated. This preliminary preparation eliminates wake-up latency while allowing the majority of the circuit to remain in low-power state.
3Adaptability or versatility
If heterogeneous chiplets are coupled, then adaptability is improved, but device complexity increases due to interface management
Solution Approach 1:
The interface circuit design with always-on and power-managed portions provides a universal solution that can be applied to heterogeneous chiplet combinations. The same interface architecture handles different chiplet types (CPU, GPU, NPU, I/O) without requiring complex custom interfaces for each pairing.
Solution Approach 2:
Despite heterogeneous chiplets, the interface methodology is homogeneous - all chiplets use the same always-on/power-managed portion architecture. This uniform approach simplifies the overall system complexity while supporting diverse chiplet types through standardized interface management.
4Speed
If bond-to-bond interface is implemented, then speed is improved by reducing latency, but device complexity increases due to interface structure
Solution Approach 1:
The bond-to-bond interface is segmented into always-on and power-managed portions. This segmentation reduces the complexity burden by allowing the critical speed-path (always-on) to be simple and fast, while the power-managed portion handles complex power management functions separately.
Data Source
AI summary
An apparatus may include a system including a plurality of integrated circuits (ICs), including a first IC having a first set of agent circuits and a second IC having a second set of agent circuits. The first IC may include a first interface with a first always-on portion and a first power-managed portion. The second IC may include a second interface coupled to the first interface, and having a second always-on portion and a second power-managed portion. A first agent circuit of the first set of agent circuits in the first IC may be configured to send, while the second IC is in a reduced power state, a transaction to a second agent circuit. The first interface may be configured to communicate, via the always-on portions of the first and second interfaces, with the second IC to cause the second IC to wake up the second agent circuit.