Chiplet Package Interposer Thinning for Tight Thickness Control

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving precise control over manufacturing tolerances for chiplet formation due to the downsizing of device dies, which requires tighter control over thickness variations and electrical intercoupling of components in advanced technology nodes.

Innovation Solution

The approach involves using a front side planarization technique to achieve a total thickness variation of less than 3 μm by flipping and thinning the interposer to expose through-silicon vias, allowing for the mounting of device dies on the backside, and forming a chiplet die stack with precise interconnect structures and encapsulation processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device dies are downsized to increase integration density, then component density is improved, but manufacturing precision control deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidthickness variation control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The interposer is divided into multiple regions with different thickness characteristics. A first region has a first thickness while a second region has a second thickness different from the first. This segmentation allows different portions of the interposer to be optimized for different functions: one region for precise thickness control and another for accommodating through-silicon vias and connectors, thereby resolving the contradiction between high integration density and manufacturing precision control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the interposer are given different local properties. The first region is designed with specific thickness characteristics suitable for mounting device dies, while the second region is designed with different thickness to accommodate through-silicon vias and connectors. This local differentiation enables precise control of thickness variation in critical areas while maintaining overall integration density.

Inventive Principle:
Principle #3Local quality

2Reliability

If through-silicon vias are used for electrical intercoupling, then electrical connection is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical intercouplingVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Through-silicon vias are formed in the interposer before the device dies are mounted. This preliminary action allows the vias to be precisely positioned and formed in the thinned region of the interposer, ensuring accurate electrical intercoupling pathways are established before the dies are attached. The connectors are also formed in advance in the same thinned region, ready to receive the dies with aligned connection structures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interposer serves as an intermediary substrate that facilitates electrical coupling between device dies. By forming through-silicon vias and connectors in the interposer's thinned region, the interposer mediates the electrical connection between multiple dies without requiring direct die-to-die bonding, thereby improving reliability while managing manufacturing complexity through a standardized intermediate platform.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If front side planarization is performed to reduce thickness variation, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvetotal thickness variationVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Instead of applying planarization processes to the front surface of the interposer, the invention addresses thickness variation by thinning the back surface of the interposer to expose through-silicon vias. This dimensional approach—removing material from the back rather than adding or planarizing the front—achieves precise thickness control (total thickness variation of less than 3 μm) while avoiding complex front-side planarization steps.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11929261B2Semiconductor package and method of manufacturing the same
Publication Date: 2024.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11929261B2 patent drawing
  • US11929261B2 patent drawing
  • US11929261B2 patent drawing

AI summary

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.