Chiplet Edge I/O Pad Layout for Rotation and Dense Cluster Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Aligning input-output (I/O) between chiplets in a chiplet system is challenging, especially in tightly packed matrices, which affects the overall performance and footprint of the system.
Innovation Solution
Implementing a chiplet architecture with a chiplet protocol interface (CPI) that uses a packet-based network for flexible and high-speed interaction, along with AIB channels and SERDES hardware for inter-chiplet communication, and a chiplet mesh network for direct connections, ensuring proper alignment and close-coupled interconnects through symmetrically arranged I/O pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If chiplets are tightly packed to reduce footprint, then area is reduced, but I/O alignment becomes more difficult
Solution Approach 1:
The chiplet design segments I/O pads into multiple blocks along each edge, with each block independently positionable. This segmentation allows the I/O interface to be divided into manageable units that can be independently aligned and rotated, making it feasible to achieve proper I/O alignment even in tightly packed chiplet configurations where traditional monolithic I/O interfaces would be difficult to align.
Solution Approach 2:
The patent employs asymmetric positioning of I/O pad blocks relative to the chiplet centerline, with blocks placed at specific distances that are half the distance between adjacent blocks. This asymmetric arrangement, combined with rotational capability, enables flexible orientation of chiplets to achieve optimal I/O alignment in tightly packed matrices, resolving the conflict between small footprint and alignment ease.
2Ease of operation
If chiplets are rotated to optimize I/O alignment, then I/O alignment is improved, but interface complexity increases
Solution Approach 1:
The patent implements a universal I/O pad block design that can serve multiple functions: it can be positioned at different locations along the edge, rotated to different orientations, and connected to various chiplet functions. This multi-functional design allows the same basic I/O block structure to adapt to different alignment requirements, reducing the need for multiple specialized interface designs and thereby managing complexity while maintaining alignment flexibility.
Solution Approach 2:
The patent changes the positional parameters of I/O pad blocks systematically - specifically placing blocks at distances from the centerline equal to half the distance between adjacent blocks. This parameter-based approach allows for standardized, predictable positioning that simplifies the rotation and alignment process, as the same set of parameter rules applies regardless of the specific chiplet configuration or rotation angle required.
Data Source
AI summary
A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.