Chiplet Edge I/O Pad Layout for Rotated Multi-Chiplet Clusters
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Solution Overview
Problem
Chiplet-based systems face challenges in aligning input-output (I/O) between chiplets, which can lead to inefficiencies in performance and footprint optimization.
Innovation Solution
The implementation of a chiplet architecture that uses a network-on-chip (NOC) with a chiplet protocol interface (CPI) to facilitate high-speed, flexible inter-chiplet communication, combined with a tightly packed matrix arrangement of chiplets and micro-bump interconnects to minimize latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chiplets are arranged in a traditional alignment manner, then I/O alignment between chiplets is simplified, but the system footprint increases and performance is reduced
Solution Approach 1:
The patent applies asymmetry by allowing chiplets to be rotated into non-traditional orientations within the cluster. Instead of requiring all chiplets to align in standard orientations, the system supports rotated placements (e.g., 90-degree rotations) that optimize spatial utilization. This asymmetric arrangement reduces the overall system footprint while the NOC infrastructure maintains proper I/O connectivity despite the non-uniform orientations.
Solution Approach 2:
The network-on-chip (NOC) acts as an intermediary that mediates between rotated chiplets and the external interface. The NOC's switch fabric and routing logic handle the complexity of connecting chiplets in various orientations, abstracting away the alignment complexity from the chiplet design itself. This intermediary infrastructure enables rotated placements without requiring complex external wiring.
2Area of stationary object
If chiplets are rotated into non-traditional orientations, then system footprint is reduced, but I/O alignment between chiplets becomes more complex
Solution Approach 1:
The system segments the I/O interface into standardized components that can be independently rotated and connected through the NOC switch fabric. Each chiplet's I/O blocks are designed as modular segments that can be oriented differently, and the NOC routing logic segments the connection paths to handle each rotated interface independently. This segmentation allows complex rotated arrangements to be managed through modular, standardized connections.
Solution Approach 2:
The patent changes the orientation parameter of chiplets within the cluster, allowing them to be placed at different angles (e.g., 0°, 90°, 180°, 270°) rather than fixed alignments. The NOC infrastructure adapts to these parameter changes by dynamically routing signals through the switch fabric to accommodate the rotated orientations, thereby reducing footprint while managing complexity through flexible parameter adjustment.
3Speed
If a network-on-chip with chiplet protocol interface is implemented, then inter-chiplet communication speed and flexibility improve, but device complexity increases
Solution Approach 1:
The network-on-chip infrastructure is designed as a universal platform that handles multiple functions: high-speed data transmission, routing between rotated chiplets, protocol conversion, and interface management. The NOC switch fabric provides multi-functional capabilities that consolidate what would otherwise require separate specialized interconnect structures, thereby improving communication speed while managing complexity through a unified multi-purpose infrastructure.
Data Source
AI summary
A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.