Chiplet Interconnect Retraining with Active Link Modules
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Solution Overview
Problem
Existing interconnect architectures between chiplets in SoCs face challenges in maintaining link reliability and integrity due to increasing bandwidth and data throughput requirements, with conventional retraining procedures being complex and inefficient, particularly when a fault occurs.
Innovation Solution
A method for retraining a failed link module in a multimodule data communication link while other link modules are active, reconfiguring the link to exclude the failed module, and restoring functionality using a reduced number of link modules, in compliance with UCIe specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional retraining procedures are used for failed link modules, then link reliability can be restored, but the retraining process is complex and causes significant downtime
Solution Approach 1:
The patent segments the retraining process into independent per-module operations rather than requiring system-wide retraining. When a link module fails, only that specific module undergoes retraining while other modules continue operating, thereby reducing overall downtime and complexity.
Solution Approach 2:
The patent implements preliminary diagnostics and isolation mechanisms that identify failed link modules before full retraining is initiated. This preliminary action allows the system to prepare retraining sequences in advance and minimize disruption to active data transmission channels.
2Reliability
If all link modules are retrained when one fails, then link integrity is ensured, but bandwidth utilization decreases during retraining
Solution Approach 1:
The patent divides the interconnect into independent link modules that can be managed separately. When one module fails, the retraining is confined to that specific module while other modules maintain full bandwidth utilization, preventing system-wide performance degradation.
Solution Approach 2:
The patent enables continuous data transmission through healthy link modules while retraining proceeds in parallel on failed modules. This maintains productivity by ensuring that functional modules continue operating at full capacity without interruption.
3Productivity
If complex interconnect architectures are used to meet bandwidth requirements, then data throughput increases, but training and repair complexity increases
Solution Approach 1:
The patent organizes the complex interconnect architecture into standardized, modular link modules with uniform interfaces and control mechanisms. This segmentation simplifies training and repair procedures by providing consistent module-level control, even as the overall system scales to meet high bandwidth requirements.
Solution Approach 2:
The patent implements universal control mechanisms that can diagnose, isolate, and retrain any link module regardless of its specific function or position in the interconnect. This multi-functional approach reduces the complexity of training and repair procedures across diverse high-bandwidth configurations.
Data Source
AI summary
An integrated circuit (IC) device, implemented using chiplets mounted on a substrate, may include a controller and a first plurality of link modules. The first plurality of link modules may be configured to provide data lanes in a multimodule data communication link. The controller may be configured to retrain a failed link module in the first plurality of link modules while one or more other link modules in the first plurality of link modules are active and available for transmitting or receiving data, reconfigure the multimodule data communication link to use a second plurality of link modules that excludes the failed link module and includes fewer link modules than the first plurality of link modules, and reconfigure the multimodule data communication link to use the first plurality of link modules for transmitting or receiving the data after the failed link module has been successfully retrained.