Chiplet Link Masking for Toggle and Power Reduction

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Solution Overview

Problem

Chiplet links in integrated circuits consume significant power due to frequent toggling between voltage states, leading to increased energy consumption, heat generation, and reduced efficiency, particularly in data centers and smaller computing systems.

Innovation Solution

Implement pre-generated masks during an offline simulation process to reduce toggle rates and power consumption by applying these masks to data before transmission, using entropy calculations to select the most effective mask based on bit patterns and energy costs, and transmitting the mask index rather than the mask itself to maintain bandwidth efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transmitted frequently over chiplet links, then data exchange capability is improved, but power consumption increases due to frequent toggling between voltage states

Engineering Contradiction:
Improvedata exchange capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by modifying the voltage state transitions of signal lanes. Instead of allowing frequent toggling between high and low voltage states, the system controls and limits the number of transitions (toggle rates) to reduce power consumption while maintaining necessary data exchange functionality through selective lane activation and data compression techniques

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If toggle rate is reduced to lower power consumption, then energy efficiency is improved, but data transmission capability may be degraded

Engineering Contradiction:
Improveenergy efficiencyVSAvoiddata transmission capability
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent segments the data transmission function across multiple lanes and uses selective activation. By dividing data into packets and transmitting only when necessary on specific lanes, the system reduces overall toggle rates while maintaining data transmission capability. Unused lanes remain idle, avoiding unnecessary power consumption from continuous toggling

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs periodic data transmission bursts rather than continuous transmission. Data is sent in scheduled packets with idle periods in between, allowing lanes to settle and reducing the frequency of voltage transitions. This periodic action pattern maintains data exchange capability while significantly reducing average power consumption

Inventive Principle:
Principle #19Periodic action

3Productivity

If more lanes are activated for data transmission, then bandwidth is improved, but heat generation increases due to higher power consumption

Engineering Contradiction:
ImprovebandwidthVSAvoidheat generation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent applies local quality by selectively activating only the necessary number of lanes based on current data transmission requirements. Instead of keeping all lanes active at full capacity, the system dynamically adjusts which lanes are in use, ensuring that bandwidth is sufficient for current needs while minimizing the number of active high-power lanes, thereby reducing overall heat generation

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250306663A1Toggle and Power Reduction for Chiplet Links
Publication Date: 2025.10.02 ADVANCED MICRO DEVICES INC
  • US20250306663A1 patent drawing
  • US20250306663A1 patent drawing
  • US20250306663A1 patent drawing

AI summary

Toggle and power reduction for chiplet links is described. In accordance with the described techniques, a mask is selected from a plurality of pre-generated masks based on a bit pattern of data to be transmitted from a first chiplet to a second chiplet via a chiplet link. Masked data are generated by applying the mask to the data at the first chiplet. The masked data are transmitted from the first chiplet to the second chiplet via the chiplet link; and the masked data are corrected at the second chiplet by inverting the mask at the second chiplet.