Chiplet Reserved Memory Access for Confidential AI Workloads
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Solution Overview
Problem
Existing systems-in-package (SiPs) face challenges in extending trust boundaries to include accelerator circuits and I/O devices, leading to performance degradation and security concerns when deploying AI workloads at the edge, due to lack of secure memory access and confidentiality, which existing confidential computing technologies like SGX, TDX, and AMD SEV are limited to core processor circuits.
Innovation Solution
A device-side security architecture is implemented to extend trust domains to integrated accelerator circuits and I/O devices within a SiP, using a reserved portion of system memory accessible via CXL.$/UCIe and CXL.IO/PCIe, ensuring secure access and confidentiality through a chiplet reserved memory (CRM) region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If confidential computing technologies (SGX, TDX, AMD SEV) are used to protect memory access, then security and confidentiality are improved, but these technologies are limited to core processor circuits only, preventing accelerator circuits and I/O devices from accessing reserved memory regions
Solution Approach 1:
The patent segments the memory access control by introducing a dedicated memory protection extension that operates independently within the trusted execution environment. This extension is divided into multiple components including a memory protection unit, access control logic, and credential verification modules, allowing different parts of the system (core processors, accelerator circuits, I/O devices) to access appropriate memory regions with proper authorization while maintaining security boundaries.
Solution Approach 2:
The patent introduces a memory protection extension as an intermediary component between the existing confidential computing technologies and the accelerator circuits/I/O devices. This extension acts as a mediator that receives memory access requests from untrusted components, verifies their credentials, and grants or denies access to reserved memory regions, thereby enabling secure access without compromising the core processor's confidential computing capabilities.
2Reliability
If memory access is restricted to core processor circuits only, then security is maintained, but performance degrades when deploying AI workloads at the edge due to lack of secure memory access for accelerator circuits
Solution Approach 1:
The patent implements preliminary action by establishing memory protection credentials and access control policies during system initialization and configuration phases. The memory protection extension is pre-configured with credential verification logic and access control rules that enable accelerator circuits and I/O devices to securely access reserved memory regions before AI workloads are deployed, eliminating performance bottlenecks while maintaining security.
Solution Approach 2:
The memory protection extension serves as an intermediary that enables accelerator circuits to access reserved memory regions securely. By implementing credential verification and access control mechanisms in this intermediary layer, the system allows AI workloads to execute on accelerator circuits with secure memory access, thereby improving productivity without compromising security.
3Adaptability or versatility
If trust boundaries are extended to include accelerator circuits and I/O devices, then adaptability for AI workloads is improved, but security concerns arise due to lack of confidential computing support for these devices
Solution Approach 1:
The patent segments the trust domain extension into controlled access zones. The memory protection extension creates distinct access control zones for different device types (accelerator circuits, I/O devices) with specific credential requirements. This segmentation allows trust boundaries to be extended adaptively to various devices while maintaining security through differentiated access control policies for each segment.
Solution Approach 2:
The patent implements feedback mechanisms through the memory protection extension that continuously monitor and verify access requests from accelerator circuits and I/O devices. The extension provides feedback by verifying credentials, enforcing access control policies, and dynamically adjusting access permissions based on verified trust levels, thereby enabling trust domain extension while maintaining security through continuous verification.
Data Source
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AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed for memory access for multi-chiplet system-in-package. Example instructions cause at least one circuit in a system-in-package (SiP) to reserve a region in a memory associated with the SiP for exclusive use by a first die of the SiP apart from a second die of the SiP. For example, the memory is for use by multiple, respective, dies of the SiP.