Chiplet Memory Layout Using Interposer Routing to Cut Signal Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of XPU devices is hindered by the large area requirements of SRAMs, which are not efficiently stacked due to technology node size differences between processing and SRAM chiplets, leading to increased costs and signal loss.
Innovation Solution
The proposed solution involves a semiconductor package structure with a processing component and storage units arranged in a specific configuration, where the first storage unit is supported by the circuit structure and electrically connected to the processing component, and the second storage unit is disposed under the circuit structure and connected via the circuit structure, allowing for efficient electrical connection and reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SRAM chiplets are stacked to increase SRAM capacity, then the SRAM capacity is improved, but the connection path between SRAM and processing chiplet increases accordingly, leading to increased signal loss and cost
Solution Approach 1:
The patent transitions from vertical stacking (3D) to lateral arrangement (2D) of SRAM chiplets. Multiple SRAM chiplets are arranged side-by-side on the same substrate plane rather than stacked vertically, which shortens the electrical connection path to the processing chiplet while maintaining increased SRAM capacity.
Solution Approach 2:
The patent introduces a circuit structure (interposer) as an intermediary component that facilitates electrical connections between multiple SRAM chiplets and the processing chiplet. This intermediary enables efficient signal routing with reduced path length compared to direct vertical stacking through TSVs.
2Area of stationary object
If SRAM chiplets are stacked on processing chiplet, then the package size is reduced, but the technology node size difference between processing and SRAM chiplets makes stacking difficult
Solution Approach 1:
Instead of vertical stacking in the Z-dimension, the patent arranges SRAM chiplets laterally in the X-Y plane. This dimensional change eliminates the need for precise vertical alignment between different technology node chiplets, significantly easing manufacturing while maintaining compact package footprint.
Solution Approach 2:
The patent segments the SRAM storage function into multiple separate SRAM chiplets arranged laterally, each connecting to the processing chiplet through the circuit structure. This segmentation allows each SRAM chiplet to be manufactured at its optimal technology node independently, avoiding the stacking difficulties caused by technology node mismatches.
3Quantity of substance
If SRAM area is increased to meet capacity requirements, then the SRAM capacity is improved, but the overall XPU floorplan miniaturization is hindered
Solution Approach 1:
The patent utilizes lateral arrangement of SRAM chiplets on the circuit structure, effectively using the planar area of the circuit structure to accommodate multiple SRAM chiplets. This approach increases SRAM capacity without proportionally increasing the overall XPU floorplan area, as the SRAM chiplets share the circuit structure substrate rather than requiring additional vertical stacking space.
Data Source
AI summary
The present disclosure provides an electronic device, which includes a circuit structure, a processing component, a first storage unit, and a second storage unit. The processing component is disposed over the circuit structure. The first storage unit is supported by the circuit structure, and electrically connected to the processing component. The second storage unit is disposed under the circuit structure and electrically connected to the processing component via the circuit structure.