Chiplet-Memory Interconnect Layout for Multi-Channel Data Transfer

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Solution Overview

Problem

Legacy memory interconnect approaches in semiconductor packages typically involve a single active die communicating with one or more memory devices, leading to inefficiencies in I/O width matching and power consumption.

Innovation Solution

The semiconductor package includes a first and second chiplet, a memory device, and an interconnect structure that couples the chiplets to different memory channels of the memory device, utilizing embedded multi-die interconnect bridges (EMIBs) or interposers to manage communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single active die communicates with one or more memory devices using legacy interconnect approaches, then the I/O width matching is simplified, but the data transfer efficiency and power consumption are suboptimal

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidI/O power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The active die is segmented into multiple chiplets (first chiplet, second chiplet, etc.), each capable of independent communication with memory devices. This segmentation allows parallel data transfers across multiple channels, improving overall data transfer efficiency while distributing power consumption across multiple smaller I/O interfaces rather than one large interface

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimensional approach by organizing chiplets and memory devices in a multi-channel parallel architecture. Instead of a single communication path, multiple independent channels are established, adding a parallelism dimension to the data transfer system. This enables simultaneous data operations across different channels, significantly boosting productivity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple chiplets are coupled to different memory channels, then data transfer efficiency improves, but the interconnect structure complexity increases

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidinterconnect structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

An interposer is introduced as an intermediary component that manages the complex interconnections between multiple chiplets and memory devices. The interposer provides a standardized interface layer that simplifies the routing and mapping of signals, making the multi-channel parallel architecture manageable despite its inherent complexity

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The interconnect structure is designed with universal, standardized interfaces that can accommodate multiple chiplet types and memory device configurations. This multi-functionality allows the same interconnect architecture to support various combinations of chiplets and memory devices, reducing the effective complexity by providing a scalable, reusable framework

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12205924B2Semiconductor packages with chiplets coupled to a memory device

Publication Date: 2025.01.21 INTEL CORP

AI summary

Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.