3D Chiplet Package Layout for Shorter Electrical Paths
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Solution Overview
Problem
Current package designs face challenges in achieving optimal performance due to inefficient coupling of integrated devices and passive components, leading to suboptimal electrical paths and increased latency, which affects the overall efficiency and cost-effectiveness of the package.
Innovation Solution
The design incorporates a metallization portion coupled with integrated devices and chiplets through pillar interconnects, allowing for reduced electrical paths and improved signal latency, while utilizing chiplets with trench capacitors for high capacitance density, enabling more compact form factors and efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If integrated devices and passive components are coupled using conventional package designs, then the package structure is simpler, but the electrical paths are longer and latency is increased
Solution Approach 1:
The package is segmented into multiple functional layers: integrated devices, chiplets, metallization portions, and encapsulation layers. This segmentation allows optimization of electrical paths between components while maintaining manageable structural complexity through modular organization.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar coupling to three-dimensional vertical stacking. Integrated devices and chiplets are positioned at different vertical levels and coupled through metallization portions, creating shorter electrical paths in the vertical dimension while organizing complexity across multiple layers.
2Power
If chiplets with trench capacitors are used, then capacitance density and power delivery efficiency are improved, but the manufacturing process becomes more complex
Solution Approach 1:
Trench capacitors are fabricated as part of the chiplet structure before the chiplet is integrated into the final package. This preliminary action allows the capacitors to be pre-formed and tested, simplifying the overall manufacturing process despite the added complexity of three-dimensional integration.
Solution Approach 2:
The chiplet structure combines multiple materials including conductive materials for trenches, dielectric materials for insulation, and semiconductor materials for active devices. This composite structure enables high capacitance density while allowing each material to be optimized for its specific function.
3Adaptability or versatility
If multiple chiplets are integrated into a single package, then functionality and performance are enhanced, but the device complexity increases
Solution Approach 1:
The package structure is designed with universal metallization portions and standardized coupling interfaces that can accommodate different types of chiplets and integrated devices. This multi-functionality allows the same package architecture to support various functional configurations without proportionally increasing complexity.
Solution Approach 2:
Multiple chiplets are nested within the package structure at different vertical levels, with each chiplet containing its own functional elements. This nesting approach allows high functionality to be achieved by stacking modular units, managing complexity through hierarchical organization rather than flat expansion.
Data Source
AI summary
A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.