Chiplet-in-Package Interconnect Layout for Lower Electrical Latency
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Solution Overview
Problem
Current package designs face challenges in achieving optimal performance due to inefficient coupling of integrated devices and passive components, leading to suboptimal electrical paths and increased latency, which affects the overall performance and cost-effectiveness of the package.
Innovation Solution
The design incorporates a package structure with a metallization portion, integrated devices, and chiplets, where the chiplets are strategically positioned close to the integrated devices using pillar interconnects and metallization layers to reduce electrical paths and latency, allowing for cost savings by utilizing different technology nodes for various components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If integrated devices and passive components are coupled using conventional package designs, then the package structure is simpler, but the electrical paths are longer and latency is increased
Solution Approach 1:
The package is segmented into multiple functional layers including a substrate, a first metallization layer with integrated devices, a second metallization layer with passive components, and interconnect structures. This segmentation allows each layer to be optimized independently for its specific function while reducing overall electrical latency through strategic component placement and direct coupling paths.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar coupling to a three-dimensional stacked architecture. Integrated devices in the first metallization layer are vertically coupled to passive components in the second metallization layer through pillar interconnects and via structures, creating direct electrical paths that reduce latency while utilizing the vertical dimension for compact integration.
2Ease of manufacture
If different technology nodes are used for integrated devices and chiplets, then cost is reduced, but manufacturing complexity increases
Solution Approach 1:
The package is divided into separately fabricable segments including integrated devices at a first technology node and chiplets at a second technology node. Each segment can be manufactured independently using optimized processes for its specific technology node, then integrated through standardized interconnect structures, thereby reducing overall manufacturing cost while managing complexity through modular assembly.
Solution Approach 2:
The patent employs universal interconnect structures such as pillar interconnects, via holes, and metallization layers that serve multiple functions: they provide electrical coupling between different technology nodes, enable mechanical support, and facilitate thermal management. This universality allows different technology nodes to be integrated using common manufacturing and assembly processes, reducing overall manufacturing complexity.
3Productivity
If chiplets are positioned close to integrated devices, then electrical paths are shortened and performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
Alignment features such as registration marks, protrusions, and recesses are incorporated into the substrate and chiplet designs before the final assembly step. These preliminary structural elements guide the precise positioning of chiplets relative to integrated devices during assembly, ensuring accurate alignment and optimal electrical coupling while reducing the precision burden on the final placement process.
Solution Approach 2:
The patent introduces intermediary structures including pillar interconnects, via holes, and metallization layers that act as mediators between integrated devices and chiplets. These intermediaries provide robust electrical coupling and mechanical support, tolerating minor positioning variations while maintaining optimal electrical performance, thereby reducing the stringency of manufacturing precision requirements.
Data Source
AI summary
A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.