Chiplet Partitioning Layout for Better Reticle Utilization
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Solution Overview
Problem
The inefficiencies in semiconductor device fabrication, particularly in photolithography processes, lead to increased costs and production time due to underutilization of reticle areas, resulting in higher energy consumption and delayed production times for semiconductor dies.
Innovation Solution
The implementation of disaggregation facilitation circuitry that determines optimal layouts for functional blocks within semiconductor dies, allowing for efficient utilization of reticle areas and flexible fabrication of chiplets, which can be combined to form larger systems, thereby reducing defects and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography processes are used with conventional reticle layouts, then semiconductor dies can be manufactured, but reticle area utilization is low leading to increased production time and energy consumption
Solution Approach 1:
The patent divides a large monolithic die into multiple smaller chiplets that can be independently fabricated on the same reticle. This segmentation allows better utilization of the reticle area by arranging multiple chiplet layouts simultaneously, reducing the number of separate fabrication runs needed and improving overall production efficiency while decreasing total production time.
2Productivity
If photolithography processes are used with conventional reticle layouts, then semiconductor dies can be manufactured, but energy consumption increases due to underutilization of reticle areas
Solution Approach 1:
By segmenting the monolithic die into multiple chiplets that can be arranged on the same reticle, the patent maximizes reticle area utilization. This reduces the number of separate photolithography exposure runs required, thereby decreasing total energy consumption while maintaining or improving production efficiency.
3Ease of manufacture
If smaller chiplets are fabricated instead of large monolithic dies, then reticle area utilization improves and production costs decrease, but additional disaggregation processes are required
Solution Approach 1:
The patent employs segmentation to divide the monolithic die into multiple chiplets, which improves reticle utilization and reduces fabrication costs. The disaggregation facilitation circuitry automatically generates the necessary layout configurations and interconnect designs, managing the added complexity through automation rather than manual processes.
Solution Approach 2:
The disaggregation facilitation circuitry acts as an intermediary tool that automates the complex tasks of generating chiplet layouts, designing interconnects, and managing the disaggregation process. This intermediary system handles the complexity of coordinating multiple chiplets while simplifying the overall manufacturing workflow.
4Productivity
If disaggregation facilitation circuitry is implemented, then optimal layouts for functional blocks can be determined and reticle utilization optimized, but additional circuitry and processing steps are added
Solution Approach 1:
The disaggregation facilitation circuitry serves as an intermediary design tool that optimizes chiplet layouts and interconnect configurations to maximize reticle utilization. While it adds circuitry components, the automation it provides in generating optimal layouts and managing the disaggregation process offsets the added complexity by improving production efficiency and reducing manual design efforts.
Data Source
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AI summary
Methods and apparatus for disaggregation of semiconductor dies in an integrated circuit package. An example apparatus includes interface circuitry, machine readable instructions, programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate an adjacency matrix for different functional blocks to be implemented in an integrated circuit, the adjacency matrix defining connections between ones of the functional blocks, and determine a group of the functional blocks to be included in a first chiplet of a plurality of chiplets for the integrated circuit, the group of the functional blocks determined based on weights assigned to the connections defined in the adjacency matrix.