Chiplet PoP Semiconductor Package for Smaller Board Footprint
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Solution Overview
Problem
The increasing demand for smaller electronic devices with large battery capacity necessitates reducing the space occupied by communication chip packages within semiconductor packages, as dividing application processors into chiplets enlarges the package size and requires separate communication chip packages.
Innovation Solution
An application processor is divided into a first and second chiplet, mounted on the lower package of a package-on-package (PoP) device, with a communication chip on the upper package, eliminating the need for a separate communication chip package and allowing efficient heat dissipation through the communication chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an application processor is divided into chiplets, then manufacturing cost is reduced and yield is improved, but the space occupied by the semiconductor package becomes larger
Solution Approach 1:
The patent implements a package-on-package (PoP) structure where a communication chip package is stacked vertically on top of a semiconductor package containing chiplets. This nesting approach allows the communication chip to be positioned above the semiconductor package, utilizing the vertical dimension rather than horizontal space, thereby reducing the overall footprint while maintaining all necessary functional components
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture by placing the communication chip package in the vertical direction above the semiconductor package. This dimensional change enables space optimization by exploiting the Z-axis (height) rather than expanding the X-Y plane area, thus reducing the board space occupied while accommodating both chiplet-based processor and communication functions
2Adaptability or versatility
If a separate communication chip package is formed, then communication functionality is provided, but the board size increases and battery space is reduced
Solution Approach 1:
The patent merges the semiconductor package containing chiplets with the communication chip package into a single integrated PoP structure. By combining these previously separate packages into one stacked unit, the overall board footprint is reduced while maintaining both the processing capabilities of the chiplets and the communication functionality of the upper package
Solution Approach 2:
The communication chip package is nested vertically on top of the semiconductor package, creating a compact integrated structure. This nesting eliminates the need for separate board mounting areas for communication chips, as they are now positioned above the processor package, thereby reducing total board size and freeing up space for larger battery capacity
3Temperature
If the communication chip is mounted on the upper package, then heat dissipation is improved and space is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the communication chip from the traditional side-by-side layout and positions it vertically above the semiconductor package. This extraction and repositioning allows heat generated by the chiplets to be dissipated more effectively through the communication chip package structure, while the modular PoP design manages the manufacturing complexity through standardized stacking processes
Data Source
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AI summary
A semiconductor package includes a first redistribution structure (120), a first chiplet (130) on the first redistribution structure (120), a second chiplet (140) on the first redistribution structure (120) and proximate the first chiplet (130) in a horizontal direction parallel to a surface of the first redistribution structure (120), a second redistribution structure (170) on the first chiplet (130) and on the second chiplet (140), and a communication chip on the second redistribution structure (170).