Chiplet Package RDL Layout for Dense 3D Interconnects
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Solution Overview
Problem
The increasing complexity of integrated circuits with multiple electronic components poses challenges in design and processing, particularly in meeting the needs of memory structures and storage system structures within chiplets.
Innovation Solution
A chip package structure is developed with a chipset, a first Redistribution Layer (RDL), and a bonding pad region, where the RDL extends and rearranges bonding pads to adapt to design requirements, and includes a multi-layer structure with Through Silicon Vias (TSVs) for vertical stacking and communication buses for signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple electronic components are integrated into integrated circuits to increase functionality, then the number of electronic components and internal structures increase, but design and processing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple independent chiplets (first chiplet, second chiplet, third chiplet) that can be separately designed, manufactured, and tested. Each chiplet contains specific functional modules, allowing independent optimization and reducing overall design complexity while maintaining high functionality through modular assembly.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking by arranging chiplets in multiple layers and connecting them through vertical interconnect structures. This dimensional change enables increased functionality and integration density without proportionally increasing processing complexity, as the stacking approach standardizes interconnection methods.
2Quantity of substance
If chiplets are packaged together through internal interconnection technology, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into independent stages: chiplet fabrication, RDL formation, TSV creation, and final assembly. Each stage can be performed by different manufacturing lines with specialized equipment, reducing the complexity burden on any single process while achieving high integration density through coordinated execution of these modular manufacturing steps.
Solution Approach 2:
The patent performs preliminary actions by pre-forming RDLs and TSVs on chiplets before final assembly. Bonding pads are extended and repositioned in advance through RDL layers, and vertical interconnect structures are prepared beforehand. This preliminary preparation simplifies the final assembly process and enables higher integration density without proportionally increasing overall manufacturing complexity.
3Adaptability or versatility
If RDL extends bonding pads and changes layout, then adaptability to design requirements improves, but processing steps increase
Solution Approach 1:
The RDL structure serves multiple functions simultaneously: it extends bonding pads to reach external connections, repositions pads to match design layouts, provides electrical interconnection between chiplets, and offers mechanical support. This multi-functionality reduces the need for separate processing steps for each function, thereby improving design adaptability without proportionally increasing processing complexity.
Data Source
AI summary
A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.