Chiplet Interconnect Retry Flits for Low-Latency Error Correction
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Solution Overview
Problem
Chiplet architectures face challenges in managing high bit error rates in chip-to-chip communications, with existing error correction mechanisms being slow or complex, and there is a need for efficient interconnect designs to achieve low latency and high bandwidth.
Innovation Solution
A retry-based error correction mechanism is implemented for chip-to-chip interfaces using Type-0 and Type-1 Flits, where Type-0 Flits carry data and Type-1 Flits are used for error correction, with a retry mechanism that includes transmitting control messages to ensure reliable data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error correction mechanisms are used in chip-to-chip interfaces, then reliability is improved, but latency increases and bandwidth decreases
Solution Approach 1:
The patent applies preliminary action by pre-configuring error correction capabilities at the physical layer before data transmission begins. The interface is designed with built-in error detection and correction mechanisms that are already in place and activated, eliminating the need for post-transmission error handling protocols. This allows errors to be corrected in real-time during transmission rather than requiring retransmission sequences, thereby reducing latency while maintaining reliability.
2Reliability
If existing error correction mechanisms are used in chip-to-chip interfaces, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges error correction functionality directly into the physical layer interface circuitry, combining what were previously separate error correction modules with the transmission interface. This integration consolidates multiple functions into a unified structure, reducing the number of separate control signals and management logic required. The error correction operations are performed inline with the data path rather than through separate complex control sequences, thereby reducing device complexity while maintaining reliability.
3Reliability
If retry-based error correction is implemented, then reliability is improved, but productivity decreases due to retransmission overhead
Solution Approach 1:
The patent extracts the error correction function from the data transmission path by implementing it at the physical layer interface rather than at higher protocol layers. This separation allows error correction to operate independently and transparently to the data flow, correcting errors in real-time without requiring data to be removed from the transmission stream for retransmission. The extraction of error handling from the main data path eliminates retransmission overhead and maintains full productivity while improving reliability.
Data Source
AI summary
Some examples described herein provide for interconnect in chiplet systems, for example system-level techniques for error correction in chip-to-chip interfaces. In an example, a method of error correction includes receiving, at a first chiplet, a data message via a set of interconnect, and transmitting a first control message that requests retransmission of the data message based on detecting an error associated with receiving the data message. The method also includes transmitting one or more instances of a second control message that indicates an idle operation at the first chiplet until the first chiplet receives a third control message that triggers an end of a retransmission mode. The method also includes transmitting a fourth control message frame indicating the end of the retransmission mode, and receiving a retransmission of the data message from the second chiplet.