Chiplet Deep Sleep Coordination for DDR Self-Refresh SoCs
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Solution Overview
Problem
The challenge of coordinating deep sleep operations across multiple chips in system-on-a-chip (SoC) architectures to enhance power savings and functionality is not adequately addressed by existing technologies, leading to inefficiencies in power management and battery life in mobile devices.
Innovation Solution
The implementation of enhanced deep sleep architectures and designs that coordinate deep sleep entry and transition operations across multiple chips, including the use of an application processor subsystem (APSS) to initiate deep sleep mode, coordinate between primary and secondary chiplets, collapse subsystems, and trigger programable boot sequence (PBS) operations through a primary power management integrated controller (PMIC) to manage power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If deep sleep mode is implemented in single-chip SoCs, then power consumption is reduced, but coordination challenges arise for meeting wake-up demands
Solution Approach 1:
The patent segments the SoC into multiple chiplets (first chiplet, second chiplet, third chiplet) that can independently enter and exit deep sleep mode. Each chiplet has its own power management capabilities, allowing granular power control. This segmentation resolves the contradiction by enabling power reduction at the chiplet level while simplifying coordination compared to whole-SoC sleep mode.
Solution Approach 2:
The patent implements preliminary actions by pre-configuring wake-up logic and power restoration sequences in each chiplet before entering deep sleep mode. The chiplets prepare their power management state and wake-up triggers in advance, so when wake-up is needed, the restoration process is already initiated or can be quickly activated, reducing coordination delays.
2Adaptability or versatility
If multiple chiplets are used in SoC architecture, then functionality is enhanced, but power management coordination becomes more difficult
Solution Approach 1:
The patent divides the SoC into independent functional chiplets (first chiplet with first functionality, second chiplet with second functionality, third chiplet with third functionality). Each chiplet can be independently powered, slept, or woken based on its specific functional requirements. This allows the system to maintain high functionality while simplifying power management coordination to only involve active chiplets.
Solution Approach 2:
Each chiplet is equipped with self-service power management capabilities, including autonomous deep sleep entry and wake-up functionality. The chiplets can independently manage their own power states without requiring complex centralized coordination, thus enhancing functionality while reducing power management complexity.
3Loss of energy
If deep sleep coordination is implemented across multiple chips, then power savings are increased, but system complexity increases
Solution Approach 1:
The patent implements segmentation by creating independent power domains for each chiplet, allowing the system to achieve deep power savings by isolating and powering down individual chiplets rather than requiring system-wide sleep coordination. This reduces the complexity of inter-chip coordination while maintaining high power savings.
Solution Approach 2:
The patent introduces dynamic power management where chiplets can transition between active and deep sleep states based on real-time operational needs. This dynamic approach allows the system to achieve maximum power savings during low-activity periods while maintaining responsiveness when needed, without requiring permanently complex coordination infrastructure.
Data Source
AI summary
This disclosure provides systems, methods, and devices for memory systems that support enhanced processing core scheduling schemes. In a first aspect, a system-on-a-chip (SoC) includes at least one processor, and a memory coupled to the at least one processor. The at least one processor is configured to cause the SoC to: initiate, by an application processor subsystem (APSS) of the SoC, deep sleep mode entry based on determining a deep sleep entry trigger has been satisfied; coordinate, between a primary chiplet and a secondary chiplet of the SoC, to collapse subsystems of the primary and secondary chiplets and to put double data rate (DDR) memory of the SoC into a self-refresh mode; trigger, by the primary chiplet, programable boot sequence (PBS) operations of a primary power management integrated controller (PMIC) of the primary chiplet; and collapse, by the primary PMIC, SoC power rails. Other aspects and features are also claimed and described.