Chiplet SoC Architecture With 3D L3 Cache and Bridge Interconnect
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Solution Overview
Problem
Current parallel graphics processing systems face limitations in efficiently processing graphics and general-purpose computations due to the complexity of graphics pipelines and the need for optimized architectures that can handle diverse workloads, such as machine learning operations and pattern analysis.
Innovation Solution
A graphics processing unit (GPU) is designed to be communicatively coupled with host processor cores, utilizing a parallel processing architecture that includes a scheduler to distribute work across multiple processing clusters, enabling efficient execution of graphics and general-purpose computations through dedicated circuitry and optimized memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single integrated GPU architecture is used to handle both graphics and general-purpose computations, then processing versatility is improved, but device complexity increases
Solution Approach 1:
The patent divides the GPU architecture into multiple independent processing clusters, each capable of handling different types of computations. This segmentation allows the system to process graphics and general-purpose computations simultaneously across different clusters, reducing the complexity burden on any single unit while maintaining versatility.
Solution Approach 2:
Each processing cluster is designed with universal functionality to handle both graphics-specific operations and general-purpose computations. The clusters can be dynamically configured and scheduled to perform different tasks based on workload requirements, eliminating the need for separate dedicated hardware for different computation types.
2Productivity
If multiple processing clusters are introduced to handle diverse workloads, then processing efficiency is improved, but architectural complexity increases
Solution Approach 1:
The patent introduces a unified scheduler as an intermediary component that manages workload distribution across multiple processing clusters. This scheduler abstracts the complexity of managing multiple clusters by providing a standardized interface for task submission and automatic workload balancing, thereby improving processing efficiency without proportionally increasing architectural complexity.
Solution Approach 2:
The processing clusters are designed with dynamic configuration capabilities, allowing them to be programmatically controlled and reconfigured based on workload requirements. This dynamic nature enables efficient handling of diverse workloads while keeping the architecture adaptable rather than statically complex.
3Reliability
If fixed function computational units are used for graphics processing, then processing reliability is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements processing clusters with universal computational units that can be programmed to perform both traditional graphics operations and general-purpose computations. This universality maintains reliability through proven graphics processing capabilities while simultaneously providing adaptability for diverse computational workloads including machine learning and pattern analysis.
Solution Approach 2:
The computational units are designed with dynamic reconfigurability, allowing them to switch between different operational modes and algorithms based on the specific task requirements. This dynamic capability enables the system to maintain reliable graphics processing while adapting to various computational paradigms without requiring separate fixed-function hardware for each workload type.
Data Source
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AI summary
The present disclosure provides an apparatus comprising a package assembly comprising a plurality of chiplets and a plurality of interconnect structures. The plurality of chiplets including a first chiplet comprising a first base chiplet coupled to a bridge interconnect and an interconnect structure. The first base chiplet including an interconnect fabric, and a first plurality of level 3 cache banks to cache data read from and transmitted to a memory, a second chiplet comprising a second base chiplet, the second chiplet coupled to the first chiplet over the bridge interconnect; and a third chiplet including a second plurality of level 3 cache banks, the third chiplet stacked on the first base chiplet in a 3D arrangement and coupled to the first base chiplet over the interconnect structure.