Chiplet Spacer Interconnect Layout for Low-Latency 3D Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for connecting function-specific chiplets in stacked semiconductor devices result in increased area and latency due to the need for through-silicon vias, which adversely affect active die regions and hinder efficient power delivery.
Innovation Solution
A semiconductor package assembly configuration where a chiplet is coupled to an interposer die with a first portion connected to the interposer's surface and a second portion cantilevered, supported by a spacer interconnect that allows signal and power delivery through the package substrate, reducing overall area and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias are used to connect chiplets in stacked semiconductor devices, then electrical connection between layers is achieved, but device area increases and latency increases
Solution Approach 1:
The patent transitions from planar side-by-side chiplet arrangement to vertical stacking configuration, utilizing the third dimension (height) to reduce the footprint area. Chiplets are connected through the thickness of the substrate rather than requiring lateral expansion, thereby achieving higher integration density without increasing device area.
Solution Approach 2:
The patent implements a nested structure where chiplets are stacked vertically within the substrate thickness, similar to nested dolls. Each chiplet is positioned at different height levels, with interconnect structures penetrating through intermediate layers to establish electrical connections, maximizing space utilization in the vertical dimension.
2Reliability
If through-silicon vias are used to connect chiplets, then electrical connection is established, but latency increases due to longer signal paths
Solution Approach 1:
The patent incorporates preliminary routing designs where interconnect structures are pre-configured within the substrate to establish direct, short-length electrical pathways between chiplets before the chiplets are fully assembled. This preliminary planning of connection routes minimizes signal path length and reduces transmission latency.
3Reliability
If through-silicon vias are used for chiplet connection, then inter-layer connectivity is achieved, but power delivery to active die regions is hindered
Solution Approach 1:
The patent segments the interconnect structures into separate functional regions: signal transmission pathways and power delivery pathways. Power delivery networks are routed through dedicated channels that do not interfere with active die regions, while signal interconnects use different pathways, thereby enabling both connectivity and efficient power distribution simultaneously.
4Ease of manufacture
If chiplets are placed side-by-side, then manufacturing is simplified, but device area increases
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to achieve high integration without requiring lateral expansion. Multiple chiplets are arranged at different height levels within the substrate, connected through vertical interconnects, thereby reducing the planar footprint while maintaining manufacturing feasibility through established 3D integration processes.
Data Source
AI summary
A semiconductor package assembly includes a package interface. An interposer die has a first surface and a second surface opposite to the first surface, where the first surface of the interposer is die positioned on the package interface. The interposer die includes a plurality of conductive connections between the first surface and second surface. A chiplet includes a connectivity region having conductive pathways, with a first portion of the connectivity region coupled to a conductive connection of the interposer die and a second portion of the connectivity region cantilevered from the interposer die.