Chiplet-Based GPU Speculative Execution for Kernel Latency
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Solution Overview
Problem
Existing architectures experience kernel-to-kernel latencies and inefficiencies in large systems with parallel thread distribution across multiple blocks, particularly in multi-tile chiplet architectures, leading to lower GPU efficiency and increased end-to-end execution times for workloads like large language models.
Innovation Solution
A chiplet architecture that supports speculative execution of workloads during workload transitions, utilizing write fences and thread preloading to reduce idle time between run phases, enabling continuous operation even in the presence of write-after-read hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel threads are distributed across multiple blocks in a chiplet architecture, then system throughput is improved, but kernel-to-kernel latencies increase and GPU efficiency decreases
Solution Approach 1:
The patent implements speculative execution where the hardware predicts the next kernel to execute and prepares it in advance. The execution unit loads the next kernel's computation graph and data before the current kernel completes, eliminating idle waiting time between kernels. This preliminary action of loading and preparing the next kernel resolves the latency issue while maintaining high throughput across distributed chiplet blocks.
Solution Approach 2:
The speculative execution mechanism ensures continuous useful computation by overlapping kernel execution phases. While one kernel is executing, the hardware is already preparing the next kernel, creating a pipeline that eliminates gaps in computation. This continuity is achieved through hardware support for predicting and executing kernels out of order, maintaining steady throughput across the distributed architecture.
2Productivity
If speculative execution is implemented to reduce idle time, then GPU efficiency is improved, but device complexity increases
Solution Approach 1:
The execution unit autonomously performs speculative execution by predicting the next kernel and loading it without requiring external intervention. The hardware self-manages the execution pipeline, automatically selecting and preparing the next computation graph based on internal heuristics. This self-service approach improves GPU efficiency while keeping the added complexity contained within the execution unit rather than requiring system-wide changes.
3Reliability
If write fences are used to manage hazards in speculative execution, then data consistency is improved, but execution speed is reduced
Solution Approach 1:
The patent applies write fences selectively at specific synchronization points in the computation graph rather than continuously. The hardware identifies critical sections where data consistency is needed and inserts fences only at those locations. This localized approach maintains data consistency for shared memory operations while minimizing the performance penalty, allowing speculative execution to proceed freely in regions where consistency constraints do not apply.
Data Source
AI summary
One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprise a memory interface, processing resources configured to execute threads of a kernel, and thread dispatch circuitry to facilitate dispatch of threads of the kernel to the processing resources. The processing resources are configured to execute threads of a first kernel, receive dispatch of threads of a second kernel for execution before completion of the first kernel as threads of the first kernel retire, execute a first phase of the second kernel during completion of execution of the first kernel, via a thread of the first kernel, signal an event via an uncached write to a global memory, and execute a second phase of the second kernel based on detection of the event via an uncached read from the global memory.